From: Tony Cheng <tony.cheng@xxxxxxx>
ASIC_DATA_LINEBUFFER_NUM:
not used. each pipe has it's own lb.
ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS:
not needed. clk_src management algorithm take care of this.
ASIC_DATA_CLOCKSOURCES_NUM:
verify correct num of clk to create is already baked in resource.
remove duplicate information from hw_asic_id.
Signed-off-by: Tony Cheng <tony.cheng at amd.com>
Acked-by: Harry Wentland <harry.wentland at amd.com>
---
.../gpu/drm/amd/dal/dc/adapter/adapter_service.c | 88 ----------------------
.../amd/dal/dc/asic_capability/asic_capability.c | 5 --
.../dc/asic_capability/carrizo_asic_capability.c | 11 ---
.../dc/asic_capability/hawaii_asic_capability.c | 9 ---
.../dc/asic_capability/polaris10_asic_capability.c | 18 -----
.../dal/dc/asic_capability/tonga_asic_capability.c | 9 ---
drivers/gpu/drm/amd/dal/dc/core/dc.c | 2 +
drivers/gpu/drm/amd/dal/dc/core/dc_link.c | 4 +-
drivers/gpu/drm/amd/dal/dc/core/dc_resource.c | 2 +-
.../gpu/drm/amd/dal/dc/dce100/dce100_resource.c | 9 ++-
.../gpu/drm/amd/dal/dc/dce110/dce110_resource.c | 40 ++++++----
.../gpu/drm/amd/dal/dc/dce112/dce112_resource.c | 32 ++++++--
drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c | 11 ++-
drivers/gpu/drm/amd/dal/dc/inc/core_dc.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/core_types.h | 1 +
drivers/gpu/drm/amd/dal/dc/inc/resource.h | 4 +-
.../amd/dal/include/adapter_service_interface.h | 20 +----
.../drm/amd/dal/include/asic_capability_types.h | 13 +---
18 files changed, 77 insertions(+), 202 deletions(-)
diff --git a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
index 57228a87d5a1..4c2c2fc164be 100644
--- a/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
+++ b/drivers/gpu/drm/amd/dal/dc/adapter/adapter_service.c
@@ -109,10 +109,8 @@ static const struct feature_source_entry feature_entry_table[] = {
{FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
{FEATURE_ENABLE_DFS_BYPASS, false, true},
{FEATURE_WIRELESS_FULL_TIMING_ADJUSTMENT, false, true},
- {FEATURE_MAX_COFUNC_NON_DP_DISPLAYS, 2, false},
{FEATURE_WIRELESS_LIMIT_720P, false, true},
{FEATURE_MODIFY_TIMINGS_FOR_WIRELESS, false, true},
- {FEATURE_SUPPORTED_HDMI_CONNECTION_NUM, 0, false},
{FEATURE_DETECT_REQUIRE_HPD_HIGH, false, true},
{FEATURE_NO_HPD_LOW_POLLING_VCC_OFF, false, true},
{FEATURE_LB_HIGH_RESOLUTION, false, true},
@@ -453,10 +451,6 @@ static bool get_feature_value_from_data_sources(
}
switch (feature_entry_table[idx].feature_id) {
- case FEATURE_MAX_COFUNC_NON_DP_DISPLAYS:
- *data = as->asic_cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS];
- break;
-
case FEATURE_WIRELESS_LIMIT_720P:
*data = as->asic_cap->caps.WIRELESS_LIMIT_TO_720P;
break;
@@ -469,11 +463,6 @@ static bool get_feature_value_from_data_sources(
*data = as->asic_cap->caps.WIRELESS_TIMING_ADJUSTMENT;
break;
- case FEATURE_SUPPORTED_HDMI_CONNECTION_NUM:
- *data =
- as->asic_cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM];
- break;
-
case FEATURE_DETECT_REQUIRE_HPD_HIGH:
*data = as->asic_cap->caps.HPD_CHECK_FOR_EDID;
break;
@@ -893,72 +882,6 @@ bool dal_adapter_service_is_device_id_supported(struct adapter_service *as,
}
/*
- * dal_adapter_service_get_clock_sources_num
- *
- * Get number of clock sources
- */
-uint8_t dal_adapter_service_get_clock_sources_num(
- struct adapter_service *as)
-{
- struct firmware_info fw_info;
- uint32_t max_clk_src = 0;
- uint32_t num = as->asic_cap->data[ASIC_DATA_CLOCKSOURCES_NUM];
- struct dc_bios *dcb = as->ctx->dc_bios;
-
- /*
- * Check is system supports the use of the External clock source
- * as a clock source for DP
- */
- enum bp_result bp_result = dcb->funcs->get_firmware_info(dcb, &fw_info);
-
- if (BP_RESULT_OK == bp_result &&
- fw_info.external_clock_source_frequency_for_dp != 0)
- ++num;
-
- /*
- * Add clock source for wireless if supported
- */
- num += (uint32_t)wireless_get_clocks_num(as);
-
- /* Check the "max number of clock sources" feature */
- if (dal_adapter_service_get_feature_value(as,
- FEATURE_MAX_CLOCK_SOURCE_NUM,
- &max_clk_src,
- sizeof(uint32_t)))
- if ((max_clk_src != 0) && (max_clk_src < num))
- num = max_clk_src;
-
- return num;
-}
-
-/*
- * dal_adapter_service_get_func_controllers_num
- *
- * Get number of controllers
- */
-uint8_t dal_adapter_service_get_func_controllers_num(
- struct adapter_service *as)
-{
- uint32_t result =
- as->asic_cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM];
-
- /* Check the "max num of controllers" feature,
- * use it for debugging purposes only */
-
- /* Limit number of controllers by OS */
-
- struct asic_feature_flags flags;
-
- flags.raw = as->asic_cap->data[ASIC_DATA_FEATURE_FLAGS];
-
- if (flags.bits.LEGACY_CLIENT &&
- (result > LEGACY_MAX_NUM_OF_CONTROLLERS))
- result = LEGACY_MAX_NUM_OF_CONTROLLERS;
-
- return result;
-}
-
-/*
* dal_adapter_service_is_feature_supported
*
* Return if a given feature is supported by the ASIC. The feature has to be
@@ -1098,17 +1021,6 @@ bool dal_adapter_service_get_firmware_info(
}
/*
- * dal_adapter_service_get_stream_engines_num
- *
- * Get number of stream engines
- */
-uint8_t dal_adapter_service_get_stream_engines_num(
- struct adapter_service *as)
-{
- return as->asic_cap->data[ASIC_DATA_DIGFE_NUM];
-}
-
-/*
* dal_adapter_service_get_feature_value
*
* Get the cached value of a given feature. This value can be a boolean, int,
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
index 3e83b1e4ab9e..24ab4a5b5232 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/asic_capability.c
@@ -54,15 +54,10 @@ static bool construct(
memset(cap->data, 0, sizeof(cap->data));
/* ASIC data */
- cap->data[ASIC_DATA_VRAM_TYPE] = init->vram_type;
cap->data[ASIC_DATA_VRAM_BITWIDTH] = init->vram_width;
- cap->data[ASIC_DATA_FEATURE_FLAGS] = init->feature_flags;
cap->runtime_flags = init->runtime_flags;
- cap->data[ASIC_DATA_REVISION_ID] = init->hw_internal_rev;
cap->data[ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE] = 10;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 4;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 1;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 25;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 200;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
index 340c1f1a41d6..d23d186c670f 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/carrizo_asic_capability.c
@@ -48,23 +48,15 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
{
uint32_t e_fuse_setting;
/* ASIC data */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 3;
- cap->data[ASIC_DATA_DIGFE_NUM] = 3;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 3;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 3;
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_DCE_VERSION] = 0x110; /* DCE 11 */
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 45;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 2;
cap->data[ASIC_DATA_MC_LATENCY] = 5000;
cap->data[ASIC_DATA_STUTTERMODE] = 0x200A;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 2;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 1;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
cap->data[ASIC_DATA_DOWNSCALE_LIMIT] = 150;
/* ASIC basic capability */
@@ -135,9 +127,6 @@ void carrizo_asic_capability_create(struct asic_capability *cap,
{
/* Stoney is the same DCE11, but only two pipes, three digs.
* and HW added 64bit back for non SG */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 2;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 2;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 2;
/*3 DP MST per connector, limited by number of pipe and number
* of Dig.*/
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 2;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
index d5eb323f5e87..6678053d4601 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/hawaii_asic_capability.c
@@ -54,11 +54,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
uint32_t mc_seq_misc0;
/* ASIC data */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_DIGFE_NUM] = 6;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
cap->data[ASIC_DATA_DCE_VERSION] = 0x80; /* DCE 8.0 */
@@ -67,7 +62,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
* in other words 246528 bits. */
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
cap->data[ASIC_DATA_MC_LATENCY] = 5000; /* units of ns */
/* StutterModeEnhanced; Quad DMIF Buffer */
@@ -75,9 +69,6 @@ void dal_hawaii_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- /* 3 HDMI support by default */
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
-
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
mc_seq_misc0 = dm_read_reg(cap->ctx, mmMC_SEQ_MISC0);
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
index 9e4fdfaaf76c..15b1f7a59066 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/polaris10_asic_capability.c
@@ -47,23 +47,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
{
uint32_t e_fuse_setting;
/* ASIC data */
- if (ASIC_REV_IS_POLARIS11_M(init->hw_internal_rev)) {
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 5;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 5;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 5;
- cap->data[ASIC_DATA_DIGFE_NUM] = 5;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 7;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 5;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 5;
- } else {
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
- cap->data[ASIC_DATA_DIGFE_NUM] = 6;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 8;
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 6;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 6;
- }
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_DCE_VERSION] = 0x112; /* DCE 11 */
@@ -76,7 +59,6 @@ void polaris10_asic_capability_create(struct asic_capability *cap,
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 100;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
diff --git a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
index 8fa4d856a134..2475de9c0bf5 100644
--- a/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
+++ b/drivers/gpu/drm/amd/dal/dc/asic_capability/tonga_asic_capability.c
@@ -47,27 +47,18 @@ void tonga_asic_capability_create(struct asic_capability *cap,
{
uint32_t e_fuse_setting;
/* ASIC data */
- cap->data[ASIC_DATA_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM] = 6;
- cap->data[ASIC_DATA_DIGFE_NUM] = 6;
- cap->data[ASIC_DATA_LINEBUFFER_NUM] = 6;
-
cap->data[ASIC_DATA_LINEBUFFER_SIZE] = 1712 * 144;
cap->data[ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY] = 70;
- cap->data[ASIC_DATA_CLOCKSOURCES_NUM] = 3;
cap->data[ASIC_DATA_MC_LATENCY] = 5000;
cap->data[ASIC_DATA_STUTTERMODE] = 0x2002;
cap->data[ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR] = 4;
cap->data[ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY] = 2;
- cap->data[ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM] = 3;
cap->data[ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN] = 300000;
cap->data[ASIC_DATA_DCE_VERSION] = 0x100; /* DCE 11 */
- cap->data[ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS] = 2;
cap->data[ASIC_DATA_MEMORYTYPE_MULTIPLIER] = 4;
cap->data[ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ] = 40;
- cap->data[ASIC_DATA_NUM_OF_VIDEO_PLANES] = 0;
/* ASIC basic capability */
cap->caps.IS_FUSION = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc.c b/drivers/gpu/drm/amd/dal/dc/core/dc.c
index 47db0fd82fe6..c66cb6607752 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc.c
@@ -504,6 +504,8 @@ static bool construct(struct core_dc *dc,
dc_ctx->driver_context = init_params->driver;
dc_ctx->dc = &dc->public;
+ dc->asic_id = init_params->asic_id;
+
/* Create logger */
logger = dal_logger_create(dc_ctx);
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
index 44ed32575b02..c2eb27a257d6 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_link.c
@@ -37,6 +37,7 @@
#include "stream_encoder.h"
#include "link_encoder.h"
#include "hw_sequencer.h"
+#include "resource.h"
#include "fixed31_32.h"
#include "adapter/adapter_service.h"
#include "include/asic_capability_interface.h"
@@ -1566,8 +1567,7 @@ bool dc_link_setup_psr(const struct dc_link *dc_link,
asic_cap->caps.SKIP_PSR_WAIT_FOR_PLL_LOCK_BIT;
psr_context.numberOfControllers =
- link->link_enc->adapter_service->asic_cap->
- data[ASIC_DATA_CONTROLLERS_NUM];
+ link->dc->res_pool->res_cap->num_timing_generator;
psr_context.rfb_update_auto_en = true;
diff --git a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
index 204b49bae9ee..276833847c4d 100644
--- a/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/core/dc_resource.c
@@ -133,10 +133,10 @@ bool resource_construct(
unsigned int num_virtual_links,
struct core_dc *dc,
struct resource_pool *pool,
- const struct resource_caps *caps,
const struct resource_create_funcs *create_funcs)
{
struct dc_context *ctx = dc->ctx;
+ const struct resource_caps *caps = pool->res_cap;
int i;
unsigned int num_audio = caps->num_audio;
struct resource_straps straps = {0};
diff --git a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
index f1ca073fcaa7..42c1eff389a3 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce100/dce100_resource.c
@@ -360,8 +360,10 @@ static const struct dce110_opp_reg_offsets dce100_opp_reg_offsets[] = {
};
static const struct resource_caps res_cap = {
+ .num_timing_generator = 6,
.num_audio = 6,
- .num_stream_encoder = 6
+ .num_stream_encoder = 6,
+ .num_pll = 3
};
#define CTX ctx
@@ -855,6 +857,7 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.adapter_srv = as;
+ pool->base.res_cap = &res_cap;
pool->base.funcs = &dce100_res_pool_funcs;
pool->base.underlay_pipe_index = -1;
@@ -936,7 +939,7 @@ static bool construct(
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
- pool->base.pipe_count = dal_adapter_service_get_func_controllers_num(as);
+ pool->base.pipe_count = res_cap.num_timing_generator;
pool->base.scaler_filter = dal_scaler_filter_create(ctx);
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
@@ -1000,7 +1003,7 @@ static bool construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
- &res_cap, &res_create_funcs))
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
index db7686842e36..6e6e2a629175 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce110/dce110_resource.c
@@ -325,9 +325,20 @@ static const struct dce110_clk_src_reg_offsets dce110_clk_src_reg_offsets[] = {
};
-static const struct resource_caps res_cap = {
- .num_audio = 3,
- .num_stream_encoder = 3
+static const struct resource_caps carrizo_resource_cap = {
+ .num_timing_generator = 3,
+ .num_video_plane = 1,
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 2,
+};
+
+static const struct resource_caps stoney_resource_cap = {
+ .num_timing_generator = 2,
+ .num_video_plane = 1,
+ .num_audio = 3,
+ .num_stream_encoder = 3,
+ .num_pll = 2,
};
#define CTX ctx
@@ -1140,6 +1151,15 @@ enum clocks_state dce110_resource_convert_clock_state_pp_to_dc(
return dc_clocks_state;
}
+const struct resource_caps *dce110_resource_cap(
+ struct hw_asic_id *asic_id)
+{
+ if (ASIC_REV_IS_STONEY(asic_id->hw_internal_rev))
+ return &stoney_resource_cap;
+ else
+ return &carrizo_resource_cap;
+}
+
static bool construct(
struct adapter_service *as,
uint8_t num_virtual_links,
@@ -1155,19 +1175,15 @@ static bool construct(
struct resource_straps straps = {0};
pool->base.adapter_srv = as;
+ pool->base.res_cap = dce110_resource_cap(&dc->asic_id);
pool->base.funcs = &dce110_res_pool_funcs;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
- pool->base.pipe_count = 3;
- pool->base.underlay_pipe_index = 3;
-
- if (ASIC_REV_IS_STONEY(asic_id.hw_internal_rev)) {
- pool->base.pipe_count = 2;
- pool->base.underlay_pipe_index = 2;
- }
+ pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
+ pool->base.underlay_pipe_index = pool->base.pipe_count;
dc->public.caps.max_downscale_ratio = 150;
dc->public.caps.i2c_speed_in_khz = 100;
@@ -1175,8 +1191,6 @@ static bool construct(
/*************************************************
* Create resources *
*************************************************/
-
-
pool->base.stream_engines.engine.ENGINE_ID_DIGA = 1;
pool->base.stream_engines.engine.ENGINE_ID_DIGB = 1;
pool->base.stream_engines.engine.ENGINE_ID_DIGC = 1;
@@ -1299,7 +1313,7 @@ static bool construct(
underlay_create(ctx, &pool->base);
if (!resource_construct(num_virtual_links, dc, &pool->base,
- &res_cap, &res_create_funcs))
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
index ab203dfd2914..485221696c26 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce112/dce112_resource.c
@@ -375,9 +375,18 @@ static const struct dce112_clk_src_reg_offsets dce112_clk_src_reg_offsets[] = {
}
};
-static const struct resource_caps res_cap = {
- .num_audio = 6,
- .num_stream_encoder = 6
+static const struct resource_caps polaris_10_resource_cap = {
+ .num_timing_generator = 6,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
+};
+
+static const struct resource_caps polaris_11_resource_cap = {
+ .num_timing_generator = 5,
+ .num_audio = 5,
+ .num_stream_encoder = 5,
+ .num_pll = 8, /* why 8? 6 combo PHY PLL + 2 regular PLLs? */
};
#define CTX ctx
@@ -1155,6 +1164,15 @@ static void bw_calcs_data_update_from_pplib(struct core_dc *dc)
dm_pp_notify_wm_clock_changes(dc->ctx, &clk_ranges);
}
+const struct resource_caps *dce112_resource_cap(
+ struct hw_asic_id *asic_id)
+{
+ if (ASIC_REV_IS_POLARIS11_M(asic_id->hw_internal_rev))
+ return &polaris_11_resource_cap;
+ else
+ return &polaris_10_resource_cap;
+}
+
static bool construct(
struct adapter_service *adapter_serv,
uint8_t num_virtual_links,
@@ -1166,14 +1184,14 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.adapter_srv = adapter_serv;
+ pool->base.res_cap = dce112_resource_cap(&dc->asic_id);
pool->base.funcs = &dce112_res_pool_funcs;
/*************************************************
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
- pool->base.pipe_count =
- dal_adapter_service_get_func_controllers_num(adapter_serv);
+ pool->base.pipe_count = pool->base.res_cap->num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 100;
@@ -1332,8 +1350,8 @@ static bool construct(
}
}
- if (!resource_construct(num_virtual_links, dc,
- &pool->base, &res_cap, &res_create_funcs))
+ if (!resource_construct(num_virtual_links, dc, &pool->base,
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
index 506b93f816df..d557fcc40ccb 100644
--- a/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
+++ b/drivers/gpu/drm/amd/dal/dc/dce80/dce80_resource.c
@@ -350,8 +350,10 @@ static const struct dce110_clk_src_reg_offsets dce80_clk_src_reg_offsets[] = {
};
static const struct resource_caps res_cap = {
- .num_audio = 6,
- .num_stream_encoder = 6
+ .num_timing_generator = 6,
+ .num_audio = 6,
+ .num_stream_encoder = 6,
+ .num_pll = 3,
};
#define CTX ctx
@@ -848,6 +850,7 @@ static bool construct(
struct dm_pp_static_clock_info static_clk_info = {0};
pool->base.adapter_srv = as;
+ pool->base.res_cap = &res_cap;
pool->base.funcs = &dce80_res_pool_funcs;
@@ -855,7 +858,7 @@ static bool construct(
* Resource + asic cap harcoding *
*************************************************/
pool->base.underlay_pipe_index = -1;
- pool->base.pipe_count = dal_adapter_service_get_func_controllers_num(as);
+ pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
@@ -986,7 +989,7 @@ static bool construct(
}
if (!resource_construct(num_virtual_links, dc, &pool->base,
- &res_cap, &res_create_funcs))
+ &res_create_funcs))
goto res_create_fail;
/* Create hardware sequencer */
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
index 826ae7a8998f..668e6c826090 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_dc.h
@@ -17,6 +17,7 @@
struct core_dc {
struct dc public;
struct dc_context *ctx;
+ struct hw_asic_id asic_id;
uint8_t link_count;
struct core_link *links[MAX_PIPES * 2];
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
index 5ae6ed603d62..2c0072265d8b 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/core_types.h
@@ -270,6 +270,7 @@ struct resource_pool {
struct irq_service *irqs;
const struct resource_funcs *funcs;
+ const struct resource_caps *res_cap;
};
struct pipe_ctx {
diff --git a/drivers/gpu/drm/amd/dal/dc/inc/resource.h b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
index 20a3b08442de..4e64e45e897b 100644
--- a/drivers/gpu/drm/amd/dal/dc/inc/resource.h
+++ b/drivers/gpu/drm/amd/dal/dc/inc/resource.h
@@ -37,8 +37,11 @@ enum dce_version resource_parse_asic_id(
struct hw_asic_id asic_id);
struct resource_caps {
+ int num_timing_generator;
+ int num_video_plane;
int num_audio;
int num_stream_encoder;
+ int num_pll;
};
struct resource_straps {
@@ -64,7 +67,6 @@ bool resource_construct(
unsigned int num_virtual_links,
struct core_dc *dc,
struct resource_pool *pool,
- const struct resource_caps *caps,
const struct resource_create_funcs *create_funcs);
struct resource_pool *dc_create_resource_pool(struct adapter_service *adapter_serv,
diff --git a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
index e9c31c32cc25..52bf06b8b507 100644
--- a/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
+++ b/drivers/gpu/drm/amd/dal/include/adapter_service_interface.h
@@ -145,18 +145,8 @@ enum adapter_feature_id {
FEATURE_SET_06_START = FEATURE_DCP_PROGRAMMING_WA,
FEATURE_SET_06_END = FEATURE_SET_06_START + 31,
- /* UInt set, 1 entry: Maximum co-functional non-DP displays */
- FEATURE_MAX_COFUNC_NON_DP_DISPLAYS = FEATURE_SET_06_END + 1,
- FEATURE_SET_07_START = FEATURE_MAX_COFUNC_NON_DP_DISPLAYS,
- FEATURE_SET_07_END = FEATURE_SET_07_START + 31,
-
- /* UInt set, 1 entry: Number of supported HDMI connection */
- FEATURE_SUPPORTED_HDMI_CONNECTION_NUM = FEATURE_SET_07_END + 1,
- FEATURE_SET_08_START = FEATURE_SUPPORTED_HDMI_CONNECTION_NUM,
- FEATURE_SET_08_END = FEATURE_SET_08_START + 31,
-
/* UInt set, 1 entry: Maximum number of controllers */
- FEATURE_MAX_CONTROLLER_NUM = FEATURE_SET_08_END + 1,
+ FEATURE_MAX_CONTROLLER_NUM = FEATURE_SET_06_END + 1,
FEATURE_SET_09_START = FEATURE_MAX_CONTROLLER_NUM,
FEATURE_SET_09_END = FEATURE_SET_09_START + 31,
@@ -336,14 +326,6 @@ bool dal_adapter_service_get_firmware_info(
struct adapter_service *as,
struct firmware_info *info);
-/* Get number of controllers */
-uint8_t dal_adapter_service_get_func_controllers_num(
- struct adapter_service *as);
-
-/* Get number of stream engines */
-uint8_t dal_adapter_service_get_stream_engines_num(
- struct adapter_service *as);
-
/* Get number of spread spectrum entries from BIOS */
uint32_t dal_adapter_service_get_ss_info_num(
struct adapter_service *as,
diff --git a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
index 7841662108e8..1f78dc9f52f3 100644
--- a/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
+++ b/drivers/gpu/drm/amd/dal/include/asic_capability_types.h
@@ -84,30 +84,19 @@ struct asic_bugs {
*/
enum asic_data {
ASIC_DATA_FIRST = 0,
- ASIC_DATA_CONTROLLERS_NUM = ASIC_DATA_FIRST,
- ASIC_DATA_FUNCTIONAL_CONTROLLERS_NUM,
- ASIC_DATA_DCE_VERSION,
+ ASIC_DATA_DCE_VERSION = ASIC_DATA_FIRST,
ASIC_DATA_DCE_VERSION_MINOR,
- ASIC_DATA_VRAM_TYPE,
ASIC_DATA_VRAM_BITWIDTH,
- ASIC_DATA_FEATURE_FLAGS,
- ASIC_DATA_LINEBUFFER_NUM,
ASIC_DATA_LINEBUFFER_SIZE,
ASIC_DATA_DRAM_BANDWIDTH_EFFICIENCY,
ASIC_DATA_MC_LATENCY,
ASIC_DATA_MC_LATENCY_SLOW,
- ASIC_DATA_CLOCKSOURCES_NUM,
ASIC_DATA_MEMORYTYPE_MULTIPLIER,
ASIC_DATA_STUTTERMODE,
ASIC_DATA_PATH_NUM_PER_DPMST_CONNECTOR,
- ASIC_DATA_MAX_COFUNC_NONDP_DISPLAYS,
- ASIC_DATA_REVISION_ID,
ASIC_DATA_MAX_UNDERSCAN_PERCENTAGE,
ASIC_DATA_VIEWPORT_PIXEL_GRANULARITY,
- ASIC_DATA_DIGFE_NUM,
- ASIC_DATA_SUPPORTED_HDMI_CONNECTION_NUM,
ASIC_DATA_MIN_DISPCLK_FOR_UNDERSCAN,
- ASIC_DATA_NUM_OF_VIDEO_PLANES,
ASIC_DATA_DEFAULT_I2C_SPEED_IN_KHZ,
ASIC_DATA_DOWNSCALE_LIMIT,
ASIC_DATA_MAX_NUMBER /* end of enum */
--
2.10.1
