> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Monk Liu > Sent: Monday, November 14, 2016 7:52 AM > To: amd-gfx at freedesktop.org > Cc: Liu, Monk > Subject: [PATCH] drm/amdgpu:impl vgt_flush for VI(V3) > > when shadowing enabled, tesselation app will trigger > vm fault because below three tesselation registers: > > VGT_TF_RING_SIZE__CI__VI, > VGT_HS_OFFCHIP_PARAM__CI__VI, > VGT_TF_MEMORY_BASE__CI__VI, > > need to be programed after vgt-flush. > > Tesselation picture vm fault disappeared after vgt-flush > introduced. > > v2:implement vgt-flush for CI & SI. > v3:move vgt flush inside of cntx_cntrl > > Change-Id: I77d87d93ce6580e559e734fb41d97ee8c59d245b > Signed-off-by: Monk Liu <Monk.Liu at amd.com> With the count sizes updated in the ring structures, this patch is: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c | 9 +++++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 13 +++++++++++++ > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 13 +++++++++++++ > 3 files changed, 35 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > index 9423501..0aacd36 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c > @@ -1463,6 +1463,13 @@ static void gfx_v6_0_ring_emit_hdp_flush(struct > amdgpu_ring *ring) > amdgpu_ring_write(ring, 0x1); > } > > +static void gfx_v6_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) > +{ > + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); > + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | > + EVENT_INDEX(0)); > +} > + > /** > * gfx_v6_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp > * > @@ -2802,6 +2809,8 @@ static uint64_t > gfx_v6_0_get_gpu_clock_counter(struct amdgpu_device *adev) > > static void gfx_v6_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t > flags) > { > + if (flags & AMDGPU_HAVE_CTX_SWITCH) { > + gfx_v6_0_ring_emit_vgt_flush(ring); > amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, > 1)); > amdgpu_ring_write(ring, 0x80000000); > amdgpu_ring_write(ring, 0); > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index bd9a6c8..493d889 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -2105,6 +2105,18 @@ static void gfx_v7_0_ring_emit_hdp_flush(struct > amdgpu_ring *ring) > amdgpu_ring_write(ring, 0x20); /* poll interval */ > } > > +static void gfx_v7_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) > +{ > + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); > + amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | > + EVENT_INDEX(4)); > + > + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); > + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | > + EVENT_INDEX(0)); > +} > + > + > /** > * gfx_v7_0_ring_emit_hdp_invalidate - emit an hdp invalidate on the cp > * > @@ -2260,6 +2272,7 @@ static void gfx_v7_ring_emit_cntxcntl(struct > amdgpu_ring *ring, uint32_t flags) > > dw2 |= 0x80000000; /* set load_enable otherwise this package is just > NOPs */ > if (flags & AMDGPU_HAVE_CTX_SWITCH) { > + gfx_v7_0_ring_emit_vgt_flush(ring); > /* set load_global_config & load_global_uconfig */ > dw2 |= 0x8001; > /* set load_cs_sh_regs */ > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index 9017803..d52f458 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -6187,6 +6187,18 @@ static void gfx_v8_0_ring_emit_hdp_flush(struct > amdgpu_ring *ring) > amdgpu_ring_write(ring, 0x20); /* poll interval */ > } > > +static void gfx_v8_0_ring_emit_vgt_flush(struct amdgpu_ring *ring) > +{ > + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); > + amdgpu_ring_write(ring, EVENT_TYPE(VS_PARTIAL_FLUSH) | > + EVENT_INDEX(4)); > + > + amdgpu_ring_write(ring, PACKET3(PACKET3_EVENT_WRITE, 0)); > + amdgpu_ring_write(ring, EVENT_TYPE(VGT_FLUSH) | > + EVENT_INDEX(0)); > +} > + > + > static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring) > { > amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); > @@ -6372,6 +6384,7 @@ static void gfx_v8_ring_emit_cntxcntl(struct > amdgpu_ring *ring, uint32_t flags) > > dw2 |= 0x80000000; /* set load_enable otherwise this package is just > NOPs */ > if (flags & AMDGPU_HAVE_CTX_SWITCH) { > + gfx_v8_0_ring_emit_vgt_flush(ring); > /* set load_global_config & load_global_uconfig */ > dw2 |= 0x8001; > /* set load_cs_sh_regs */ > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
