On 08/11/16 05:31 AM, Dave Airlie wrote: > On 7 November 2016 at 19:21, Christian König <deathsimple at vodafone.de> wrote: >> From: Christian König <christian.koenig at amd.com> >> >> We don't need to use the PCI BAR on APUs. This allows us to access >> the full VRAM directly without being limited by the BAR size. > > I'm feeling coherency issues, has this approach been validated with the hw team? I raised this concern internally as well, but the response indicated that it should be fine. Apparently x86 defines that write-combined writes complete before any access to UC memory (such as writing to an MMIO register or doorbell to submit a GPU operation). -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Mesa and X developer
