[PATCH libdrm 1/2] amdgpu: add SI support

[maraeo@xxxxxxxxx (Marek Olšák)]

From: Ronie Salgado <roniesalg@xxxxxxxxx>

---
 amdgpu/amdgpu_gpu_info.c | 18 +++++++++++-------
 include/drm/amdgpu_drm.h |  1 +
 2 files changed, 12 insertions(+), 7 deletions(-)

diff --git a/amdgpu/amdgpu_gpu_info.c b/amdgpu/amdgpu_gpu_info.c
index 0cc17f1..5c1644b 100644
--- a/amdgpu/amdgpu_gpu_info.c
+++ b/amdgpu/amdgpu_gpu_info.c
@@ -180,35 +180,39 @@ drm_private int amdgpu_query_gpu_info_init(amdgpu_device_handle dev)
 			return r;
 		/* extract bitfield CC_RB_BACKEND_DISABLE.BACKEND_DISABLE */
 		dev->info.backend_disable[i] =
 			(dev->info.backend_disable[i] >> 16) & 0xff;
 
 		r = amdgpu_read_mm_registers(dev, 0xa0d4, 1, instance, 0,
 					     &dev->info.pa_sc_raster_cfg[i]);
 		if (r)
 			return r;
 
-		r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
+		if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+			r = amdgpu_read_mm_registers(dev, 0xa0d5, 1, instance, 0,
 					     &dev->info.pa_sc_raster_cfg1[i]);
-		if (r)
-			return r;
+			if (r)
+				return r;
+		}
 	}
 
 	r = amdgpu_read_mm_registers(dev, 0x2644, 32, 0xffffffff, 0,
 				     dev->info.gb_tile_mode);
 	if (r)
 		return r;
 
-	r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
-				     dev->info.gb_macro_tile_mode);
-	if (r)
-		return r;
+	if (dev->info.family_id >= AMDGPU_FAMILY_CI) {
+		r = amdgpu_read_mm_registers(dev, 0x2664, 16, 0xffffffff, 0,
+					     dev->info.gb_macro_tile_mode);
+		if (r)
+			return r;
+	}
 
 	r = amdgpu_read_mm_registers(dev, 0x263e, 1, 0xffffffff, 0,
 				     &dev->info.gb_addr_cfg);
 	if (r)
 		return r;
 
 	r = amdgpu_read_mm_registers(dev, 0x9d8, 1, 0xffffffff, 0,
 				     &dev->info.mc_arb_ramcfg);
 	if (r)
 		return r;
diff --git a/include/drm/amdgpu_drm.h b/include/drm/amdgpu_drm.h
index fbdd118..62e8682 100644
--- a/include/drm/amdgpu_drm.h
+++ b/include/drm/amdgpu_drm.h
@@ -630,16 +630,17 @@ struct drm_amdgpu_info_hw_ip {
 	uint32_t  ib_size_alignment;
 	/** Bitmask of available rings. Bit 0 means ring 0, etc. */
 	uint32_t  available_rings;
 	uint32_t  _pad;
 };
 
 /*
  * Supported GPU families
  */
 #define AMDGPU_FAMILY_UNKNOWN			0
+#define AMDGPU_FAMILY_SI			100 /* Tahiti, Pitcairn, CapeVerde, Oland, Hainan */
 #define AMDGPU_FAMILY_CI			120 /* Bonaire, Hawaii */
 #define AMDGPU_FAMILY_KV			125 /* Kaveri, Kabini, Mullins */
 #define AMDGPU_FAMILY_VI			130 /* Iceland, Tonga */
 #define AMDGPU_FAMILY_CZ			135 /* Carrizo */
 
 #endif
-- 
2.7.4