if it is required, we can continue to optimize driver in the future.
Thanks
JimQu
________________________________________
å??件人: Zhu, Rex
å??é??æ?¶é?´: 2016å¹´8æ??18æ?¥ 23:24:19
�件人: Christian König; Qu, Jim; amd-gfx at lists.freedesktop.org
主�: Re: [PATCH] drm/amd/amdgpu: S3 resumed failed after 4-5 times loop
do we need to check those status(lmi status,firmware loaded, vce status and etc) when vce suspend?
it is weird that we didn't implement vce suspend function as hw spec suggested.
Best Regards
Rex
________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Christian König <deathsimple at vodafone.de>
Sent: Thursday, August 18, 2016 9:27:57 PM
To: Qu, Jim; amd-gfx at lists.freedesktop.org
Subject: Re: [PATCH] drm/amd/amdgpu: S3 resumed failed after 4-5 times loop
Am 18.08.2016 um 14:42 schrieb jimqu:
> phenomenon: software hang when device resume back, read UVD fence is 0xffffffff
> and read pcie pid is 0xffff.
> the issue is caused by VCE reset when update cg setting. according to HW programming
> guide, adjust update VCE cg sequence.
>
> Change-Id: I18b12eea21c045908cdd23f93a0b196b87bfed6c
> Signed-off-by: JimQu <Jim.Qu at amd.com>
You should probably note in the commit log that this only applies to
systems with VCE2, e.g. CIK.
Additional to that please make sure that it applies cleanly to the
amd-staging-4.6 branch.
With that made sure the patch is Reviewed-by: Christian König
<christian.koenig at amd.com>
Regards,
Christian.
> ---
> drivers/gpu/drm/amd/amdgpu/vce_v2_0.c | 123 +++++++++++++++++++++++-----------
> 1 file changed, 84 insertions(+), 39 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> index 9e70df9..6ce7c07 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vce_v2_0.c
> @@ -40,10 +40,12 @@
> #define VCE_V2_0_FW_SIZE (256 * 1024)
> #define VCE_V2_0_STACK_SIZE (64 * 1024)
> #define VCE_V2_0_DATA_SIZE (23552 * AMDGPU_MAX_VCE_HANDLES)
> +#define VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK 0x02
>
> static void vce_v2_0_mc_resume(struct amdgpu_device *adev);
> static void vce_v2_0_set_ring_funcs(struct amdgpu_device *adev);
> static void vce_v2_0_set_irq_funcs(struct amdgpu_device *adev);
> +static int vce_v2_0_wait_for_idle(void *handle);
>
> /**
> * vce_v2_0_ring_get_rptr - get read pointer
> @@ -96,6 +98,49 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
> WREG32(mmVCE_RB_WPTR2, ring->wptr);
> }
>
> +static int vce_v2_0_lmi_clean(struct amdgpu_device *adev)
> +{
> + int i, j;
> +
> + for (i = 0; i < 10; ++i) {
> + for (j = 0; j < 100; ++j) {
> + uint32_t status = RREG32(mmVCE_LMI_STATUS);
> +
> + if (status & 0x337f)
> + return 0;
> + mdelay(10);
> + }
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> +static int vce_v2_0_firmware_loaded(struct amdgpu_device *adev)
> +{
> + int i, j;
> +
> + for (i = 0; i < 10; ++i) {
> + for (j = 0; j < 100; ++j) {
> + uint32_t status = RREG32(mmVCE_STATUS);
> +
> + if (status & VCE_STATUS_VCPU_REPORT_FW_LOADED_MASK)
> + return 0;
> + mdelay(10);
> + }
> +
> + DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
> + WREG32_P(mmVCE_SOFT_RESET,
> + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
> + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
> + mdelay(10);
> + WREG32_P(mmVCE_SOFT_RESET, 0,
> + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
> + mdelay(10);
> + }
> +
> + return -ETIMEDOUT;
> +}
> +
> /**
> * vce_v2_0_start - start VCE block
> *
> @@ -106,7 +151,7 @@ static void vce_v2_0_ring_set_wptr(struct amdgpu_ring *ring)
> static int vce_v2_0_start(struct amdgpu_device *adev)
> {
> struct amdgpu_ring *ring;
> - int i, j, r;
> + int r;
>
> vce_v2_0_mc_resume(adev);
>
> @@ -137,26 +182,7 @@ static int vce_v2_0_start(struct amdgpu_device *adev)
>
> WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
>
> - for (i = 0; i < 10; ++i) {
> - uint32_t status;
> - for (j = 0; j < 100; ++j) {
> - status = RREG32(mmVCE_STATUS);
> - if (status & 2)
> - break;
> - mdelay(10);
> - }
> - r = 0;
> - if (status & 2)
> - break;
> -
> - DRM_ERROR("VCE not responding, trying to reset the ECPU!!!\n");
> - WREG32_P(mmVCE_SOFT_RESET, VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
> - ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
> - mdelay(10);
> - WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
> - mdelay(10);
> - r = -1;
> - }
> + r = vce_v2_0_firmware_loaded(adev);
>
> /* clear BUSY flag */
> WREG32_P(mmVCE_STATUS, 0, ~1);
> @@ -338,31 +364,50 @@ static void vce_v2_0_set_sw_cg(struct amdgpu_device *adev, bool gated)
>
> static void vce_v2_0_set_dyn_cg(struct amdgpu_device *adev, bool gated)
> {
> - u32 orig, tmp;
> + if (vce_v2_0_wait_for_idle(adev)) {
> + DRM_INFO("VCE is busy, Can't set clock gateing");
> + return;
> + }
>
> - tmp = RREG32(mmVCE_CLOCK_GATING_B);
> - tmp &= ~0x00060006;
> + WREG32_P(mmVCE_LMI_CTRL2, 0x100, ~0x100);
> +
> + if (vce_v2_0_lmi_clean(adev)) {
> + DRM_INFO("LMI is busy, Can't set clock gateing");
> + return;
> + }
> +
> + WREG32_P(mmVCE_VCPU_CNTL, 0, ~VCE_VCPU_CNTL__CLK_EN_MASK);
> + WREG32_P(mmVCE_SOFT_RESET,
> + VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK,
> + ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
> + WREG32(mmVCE_STATUS, 0);
> +
> + if (gated)
> + WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
> + /* LMI_MC/LMI_UMC always set in dynamic, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {0, 0} */
> if (gated) {
> - tmp |= 0xe10000;
> + /* Force CLOCK OFF , set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {*, 1} */
> + WREG32(mmVCE_CLOCK_GATING_B, 0xe90010);
> } else {
> - tmp |= 0xe1;
> - tmp &= ~0xe10000;
> + /* Force CLOCK ON, set {CGC_*_GATE_MODE, CGC_*_SW_GATE} = {1, 0} */
> + WREG32(mmVCE_CLOCK_GATING_B, 0x800f1);
> }
> - WREG32(mmVCE_CLOCK_GATING_B, tmp);
>
> - orig = tmp = RREG32(mmVCE_UENC_CLOCK_GATING);
> - tmp &= ~0x1fe000;
> - tmp &= ~0xff000000;
> - if (tmp != orig)
> - WREG32(mmVCE_UENC_CLOCK_GATING, tmp);
> + /* Set VCE_UENC_CLOCK_GATING always in dynamic mode {*_FORCE_ON, *_FORCE_OFF} = {0, 0}*/;
> + WREG32(mmVCE_UENC_CLOCK_GATING, 0x40);
>
> - orig = tmp = RREG32(mmVCE_UENC_REG_CLOCK_GATING);
> - tmp &= ~0x3fc;
> - if (tmp != orig)
> - WREG32(mmVCE_UENC_REG_CLOCK_GATING, tmp);
> + /* set VCE_UENC_REG_CLOCK_GATING always in dynamic mode */
> + WREG32(mmVCE_UENC_REG_CLOCK_GATING, 0x00);
>
> - if (gated)
> - WREG32(mmVCE_CGTT_CLK_OVERRIDE, 0);
> + WREG32_P(mmVCE_LMI_CTRL2, 0, ~0x100);
> + if(!gated) {
> + WREG32_P(mmVCE_VCPU_CNTL, VCE_VCPU_CNTL__CLK_EN_MASK, ~VCE_VCPU_CNTL__CLK_EN_MASK);
> + mdelay(100);
> + WREG32_P(mmVCE_SOFT_RESET, 0, ~VCE_SOFT_RESET__ECPU_SOFT_RESET_MASK);
> +
> + vce_v2_0_firmware_loaded(adev);
> + WREG32_P(mmVCE_STATUS, 0, ~VCE_STATUS__JOB_BUSY_MASK);
> + }
> }
>
> static void vce_v2_0_disable_cg(struct amdgpu_device *adev)
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