On Wed, Aug 10, 2016 at 3:17 AM, Christian König
<deathsimple at vodafone.de> wrote:
> Am 10.08.2016 um 09:02 schrieb Alexandre Demers:
>>
>> Signed-off-by: Alexandre Demers <alexandre.f.demers at gmail.com>
>
>
> Reviewed-by: Christian König <christian.koenig at amd.com>
Applied. Thanks!
Alex
>
>
>> ---
>> drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 +++-----
>> 1 file changed, 3 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> index 4fdfab1..3ff1258 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
>> @@ -1613,7 +1613,7 @@ static void dce_v8_0_afmt_update_ACR(struct
>> drm_encoder *encoder, uint32_t clock
>> struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
>> uint32_t offset = dig->afmt->offset;
>> - WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz <<
>> HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
>> + WREG32(mmHDMI_ACR_32_0 + offset, (acr.cts_32khz <<
>> HDMI_ACR_32_0__HDMI_ACR_CTS_32__SHIFT));
>> WREG32(mmHDMI_ACR_32_1 + offset, acr.n_32khz);
>> WREG32(mmHDMI_ACR_44_0 + offset, (acr.cts_44_1khz <<
>> HDMI_ACR_44_0__HDMI_ACR_CTS_44__SHIFT));
>> @@ -1999,7 +1999,7 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc
>> *crtc,
>> case DRM_FORMAT_XRGB4444:
>> case DRM_FORMAT_ARGB4444:
>> fb_format = ((GRPH_DEPTH_16BPP <<
>> GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
>> - (GRPH_FORMAT_ARGB1555 <<
>> GRPH_CONTROL__GRPH_FORMAT__SHIFT));
>> + (GRPH_FORMAT_ARGB4444 <<
>> GRPH_CONTROL__GRPH_FORMAT__SHIFT));
>> #ifdef __BIG_ENDIAN
>> fb_swap = (GRPH_ENDIAN_8IN16 <<
>> GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
>> #endif
>> @@ -2653,7 +2653,7 @@ static void dce_v8_0_crtc_disable(struct drm_crtc
>> *crtc)
>> case ATOM_PPLL2:
>> /* disable the ppll */
>> amdgpu_atombios_crtc_program_pll(crtc,
>> amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
>> - 0, 0, ATOM_DISABLE, 0, 0, 0, 0,
>> 0, false, &ss);
>> + 0, 0, ATOM_DISABLE, 0,
>> 0, 0, 0, 0, false, &ss);
>> break;
>> case ATOM_PPLL0:
>> /* disable the ppll */
>> @@ -3236,7 +3236,6 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device
>> *adev,
>> drm_handle_vblank(adev->ddev, crtc);
>> }
>> DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
>> -
>> break;
>> case 1: /* vline */
>> if (disp_int & interrupt_status_offsets[crtc].vline)
>> @@ -3245,7 +3244,6 @@ static int dce_v8_0_crtc_irq(struct amdgpu_device
>> *adev,
>> DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
>> DRM_DEBUG("IH: D%d vline\n", crtc + 1);
>> -
>> break;
>> default:
>> DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id,
>> entry->src_data);
>
>
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx at lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
