Looks good to me. Reviewed-by: Eric Huang <JinhuiEric.Huang at amd.com>
Regards,
Eric
On 07/18/2016 12:59 PM, Rex Zhu wrote:
> Change-Id: I4e09b1c1685657c68a1b4a73928bcaf0ac025d7d
> Signed-off-by: Rex Zhu <Rex.Zhu at amd.com>
> ---
> .../powerplay/hwmgr/polaris10_clockpowergating.c | 14 +++++++--
> .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c | 34 +++++++---------------
> .../gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h | 2 +-
> 3 files changed, 22 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
> index aeec25c..3d324d8 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c
> @@ -131,11 +131,19 @@ int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate)
>
> data->vce_power_gated = bgate;
>
> - if (bgate)
> + if (bgate) {
> + cgs_set_clockgating_state(hwmgr->device,
> + AMD_IP_BLOCK_TYPE_VCE,
> + AMD_CG_STATE_GATE);
> + polaris10_update_vce_dpm(hwmgr, true);
> polaris10_phm_powerdown_vce(hwmgr);
> - else
> + } else {
> polaris10_phm_powerup_vce(hwmgr);
> -
> + polaris10_update_vce_dpm(hwmgr, false);
> + cgs_set_clockgating_state(hwmgr->device,
> + AMD_IP_BLOCK_TYPE_VCE,
> + AMD_CG_STATE_UNGATE);
> + }
> return 0;
> }
>
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> index 5370c0f..ab3151a 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c
> @@ -4422,25 +4422,20 @@ int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
> return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate);
> }
>
> -static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
> +int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate)
> {
> - const struct phm_set_power_state_input *states =
> - (const struct phm_set_power_state_input *)input;
> struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend);
> - const struct polaris10_power_state *polaris10_nps =
> - cast_const_phw_polaris10_power_state(states->pnew_state);
> - const struct polaris10_power_state *polaris10_cps =
> - cast_const_phw_polaris10_power_state(states->pcurrent_state);
> -
> uint32_t mm_boot_level_offset, mm_boot_level_value;
> struct phm_ppt_v1_information *table_info =
> (struct phm_ppt_v1_information *)(hwmgr->pptable);
>
> - if (polaris10_nps->vce_clks.evclk > 0 &&
> - (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) {
> -
> - data->smc_state_table.VceBootLevel =
> + if (!bgate) {
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
> + PHM_PlatformCaps_StablePState))
> + data->smc_state_table.VceBootLevel =
> (uint8_t) (table_info->mm_dep_table->count - 1);
> + else
> + data->smc_state_table.VceBootLevel = 0;
>
> mm_boot_level_offset = data->dpm_table_start +
> offsetof(SMU74_Discrete_DpmTable, VceBootLevel);
> @@ -4453,18 +4448,14 @@ static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input)
> cgs_write_ind_register(hwmgr->device,
> CGS_IND_REG__SMC, mm_boot_level_offset, mm_boot_level_value);
>
> - if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
> + if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState))
> smum_send_msg_to_smc_with_parameter(hwmgr->smumgr,
> PPSMC_MSG_VCEDPM_SetEnabledMask,
> (uint32_t)1 << data->smc_state_table.VceBootLevel);
> -
> - polaris10_enable_disable_vce_dpm(hwmgr, true);
> - } else if (polaris10_nps->vce_clks.evclk == 0 &&
> - polaris10_cps != NULL &&
> - polaris10_cps->vce_clks.evclk > 0)
> - polaris10_enable_disable_vce_dpm(hwmgr, false);
> }
>
> + polaris10_enable_disable_vce_dpm(hwmgr, !bgate);
> +
> return 0;
> }
>
> @@ -4651,11 +4642,6 @@ static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i
> "Failed to generate DPM level enabled mask!",
> result = tmp_result);
>
> - tmp_result = polaris10_update_vce_dpm(hwmgr, input);
> - PP_ASSERT_WITH_CODE((0 == tmp_result),
> - "Failed to update VCE DPM!",
> - result = tmp_result);
> -
> tmp_result = polaris10_update_sclk_threshold(hwmgr);
> PP_ASSERT_WITH_CODE((0 == tmp_result),
> "Failed to update SCLK threshold!",
> diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
> index 402f5c0..dabbb5d 100644
> --- a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
> +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h
> @@ -353,6 +353,6 @@ int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr);
> int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate);
> int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate);
> int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable);
> -
> +int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, bool bgate);
> #endif
>
