Disregard that I wasn't printing out the bo_offset but the FW offset.
Tom
________________________________
From: StDenis, Tom
Sent: Friday, July 15, 2016 13:08
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: disable GFX PG on CZ/BR/ST
I threw a printk in there and got
[ 3415.512743] ME 0, off=2048, size=96
[ 3415.512747] ME 1, off=4096, size=96 <--- PFP
[ 3415.512748] ME 2, off=4096, size=96 <--- ME
[ 3415.512749] ME 3, off=65536, size=96 <--- MEC
[ 3415.512751] ME 4, off=65536, size=96 <--- MEC2
MEC/MEC2 having the same offset and pfp/me having the same seems kinda suspicious no?
It means they're overwriting each other.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of StDenis, Tom <Tom.StDenis at amd.com>
Sent: Friday, July 15, 2016 12:59
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: disable GFX PG on CZ/BR/ST
Do we know for a fact the jump tables are being initialized properly? They're only used on CZ/ST with PG turned on so it's entirely possible that code is buggy.
I don't like the aliasing the structs in amdgpu_ucode.h to random binary data specially since they have no packed pragma's attached. We should either deserialize the firmware properly (implicitly load the struct members) or add a pragma.
Tom
________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of StDenis, Tom <Tom.StDenis at amd.com>
Sent: Friday, July 15, 2016 12:25
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: Re: [PATCH] drm/amdgpu: disable GFX PG on CZ/BR/ST
Reviewed-by: Tom St Denis <tom.stdenis at amd.com>
________________________________
From: amd-gfx <amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx> on behalf of Alex Deucher <alexdeucher at gmail.com>
Sent: Friday, July 15, 2016 12:08
To: amd-gfx at lists.freedesktop.org
Cc: Deucher, Alexander
Subject: [PATCH] drm/amdgpu: disable GFX PG on CZ/BR/ST
Still some stability issues under certain workloads.
Signed-off-by: Alex Deucher <alexander.deucher at amd.com>
---
drivers/gpu/drm/amd/amdgpu/vi.c | 14 --------------
1 file changed, 14 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c
index cda7def..03a31c5 100644
--- a/drivers/gpu/drm/amd/amdgpu/vi.c
+++ b/drivers/gpu/drm/amd/amdgpu/vi.c
@@ -1249,15 +1249,7 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS;
- /* rev0 hardware doesn't support PG */
adev->pg_flags = 0;
- if (adev->rev_id != 0x00)
- adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
- AMD_PG_SUPPORT_GFX_SMG |
- AMD_PG_SUPPORT_GFX_DMG |
- AMD_PG_SUPPORT_CP |
- AMD_PG_SUPPORT_RLC_SMU_HS |
- AMD_PG_SUPPORT_GFX_PIPELINE;
adev->external_rev_id = adev->rev_id + 0x1;
break;
case CHIP_STONEY:
@@ -1276,12 +1268,6 @@ static int vi_common_early_init(void *handle)
AMD_CG_SUPPORT_HDP_LS |
AMD_CG_SUPPORT_SDMA_MGCG |
AMD_CG_SUPPORT_SDMA_LS;
- adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
- AMD_PG_SUPPORT_GFX_SMG |
- AMD_PG_SUPPORT_GFX_DMG |
- AMD_PG_SUPPORT_GFX_PIPELINE |
- AMD_PG_SUPPORT_CP |
- AMD_PG_SUPPORT_RLC_SMU_HS;
adev->external_rev_id = adev->rev_id + 0x1;
break;
default:
--
2.5.5
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