On asic powerup, the UVD clocks are not gated IIRC. All the blocks that support clockgating get gated in amdgpu_late_init() in amdgpu_device which calls the set_clockgating_state() callback for each IP. So they should be gated at that point. You'll probably want to check and see what powerplay does in it's set_clockgating_state or late_init IP callbacks. UVD and VCE are a bit trickier since they only support manual clock and powergating. Alex From: amd-gfx [mailto:amd-gfx-bounces@xxxxxxxxxxxxxxxxxxxxx] On Behalf Of StDenis, Tom Sent: Thursday, July 14, 2016 10:05 AM To: amd-gfx list Subject: powerplay UVD CG (defaults to on) Upon loading the module the UVD clocks are full on until you use the UVD block in which case CG kicks in. This is on a boot with pg_mask=0 but cg_mask left alone (I'm trying to see if I can get a system hang with PG alone turned off). That's probably a bug in powerplay though right? I'd think on boot the UVD clocks should gate. Is that on purpose or as a workaround for something? Tom -------------- next part -------------- An HTML attachment was scrubbed... URL: <https://lists.freedesktop.org/archives/amd-gfx/attachments/20160714/31d41c08/attachment-0001.html>
