They are used before/after gpu soft reset to prepare/resume engines.
Change-Id: I775a6a164093c303251b99f84eca53301aee5e44
Signed-off-by: Chunming Zhou <David1.Zhou at amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 37 ++++++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index f825311..d8c7339 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -1950,6 +1950,41 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
return 0;
}
+static int amdgpu_pre_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
+{
+ int i, r = 0;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_block_status[i].valid)
+ continue;
+ if (adev->ip_blocks[i].funcs->pre_soft_reset) {
+ r = adev->ip_blocks[i].funcs->pre_soft_reset(
+ adev, reset_mask);
+ if (r)
+ return r;
+ }
+ }
+ return r;
+}
+
+static int amdgpu_post_soft_reset(struct amdgpu_device *adev, u32 reset_mask)
+{
+ int i, r = 0;
+
+ for (i = 0; i < adev->num_ip_blocks; i++) {
+ if (!adev->ip_block_status[i].valid)
+ continue;
+ if (adev->ip_blocks[i].funcs->post_soft_reset) {
+ r = adev->ip_blocks[i].funcs->post_soft_reset(
+ adev, reset_mask);
+ if (r)
+ return r;
+ }
+ }
+ return r;
+}
+
+
/**
* amdgpu_gpu_reset - reset the asic
*
@@ -1996,7 +2031,9 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
(AMDGPU_RESET_MC | AMDGPU_RESET_VMC | AMDGPU_RESET_DISPLAY))
need_full_reset = true;
if (!need_full_reset) {
+ amdgpu_pre_soft_reset(adev, reset_mask);
amdgpu_gpu_soft_reset(adev, reset_mask);
+ amdgpu_post_soft_reset(adev, reset_mask);
reset_mask = amdgpu_asic_check_soft_reset(adev);
/* ? VCE always busy ?*/
if (reset_mask & ~AMDGPU_RESET_VCE) {
--
1.9.1
