> -----Original Message----- > From: amd-gfx [mailto:amd-gfx-bounces at lists.freedesktop.org] On Behalf > Of Ken Wang > Sent: Wednesday, July 06, 2016 10:00 PM > To: amd-gfx at lists.freedesktop.org > Cc: Wang, Qingqing > Subject: [PATCH] drm/amdgpu: Add a missing register to Polaris golden > setting > > Change-Id: I853cc261623523315e221c9a2c9ec626326e2d11 > Signed-off-by: Ken Wang <Qingqing.Wang at amd.com> > --- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index dbef1ed..159fcd2 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -1,4 +1,5 @@ > /* > +#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6 This looks like a typo and should be dropped. With that fixed: Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > * Copyright 2014 Advanced Micro Devices, Inc. > * > * Permission is hereby granted, free of charge, to any person obtaining a > @@ -282,6 +283,7 @@ static const u32 golden_settings_polaris11_a11[] = > mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f3, > mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, > mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, > + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, > }; > > static const u32 polaris11_golden_common_all[] = > @@ -312,6 +314,7 @@ static const u32 golden_settings_polaris10_a11[] = > mmTCC_CTRL, 0x00100000, 0xf31fff7f, > mmTCP_ADDR_CONFIG, 0x000003ff, 0x000000f7, > mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, > + mmVGT_RESET_DEBUG, 0x00000004, 0x00000004, > }; > > static const u32 polaris10_golden_common_all[] = > -- > 2.7.4 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
