On Wed, Jul 6, 2016 at 5:55 AM, Rex Zhu <Rex.Zhu at amd.com> wrote: > From: Ken Wang <Qingqing.Wang at amd.com> > > Signed-off-by: Ken Wang <Qingqing.Wang at amd.com> > > Change-Id: I0d17b7f6ddd5d526c9b5c38c4a28f9302fc57a44 > Reviewed-by: Alex Deucher <alexander.deucher at amd.com> Reviewed-by: Alex Deucher <alexander.deucher at amd.com> > --- > .../drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h | 22 ---------------------- > 1 file changed, 22 deletions(-) > > diff --git a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h > index 64a1953..a43754e 100644 > --- a/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h > +++ b/drivers/gpu/drm/amd/include/asic_reg/gca/gfx_8_0_sh_mask.h > @@ -8730,8 +8730,6 @@ > #define RLC_GPM_STAT__DYN_CU_POWERING_DOWN__SHIFT 0x10 > #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE_MASK 0x20000 > #define RLC_GPM_STAT__ABORTED_PD_SEQUENCE__SHIFT 0x11 > -#define RLC_GPM_STAT__RESERVED_MASK 0xfc0000 > -#define RLC_GPM_STAT__RESERVED__SHIFT 0x12 > #define RLC_GPM_STAT__PG_ERROR_STATUS_MASK 0xff000000 > #define RLC_GPM_STAT__PG_ERROR_STATUS__SHIFT 0x18 > #define RLC_GPU_CLOCK_32_RES_SEL__RES_SEL_MASK 0x3f > @@ -9104,8 +9102,6 @@ > #define RLC_GPM_LOG_CONT__CONT__SHIFT 0x0 > #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK 0xff > #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT 0x0 > -#define RLC_PG_DELAY_3__RESERVED_MASK 0xffffff00 > -#define RLC_PG_DELAY_3__RESERVED__SHIFT 0x8 > #define RLC_GPM_INT_DISABLE_TH0__DISABLE_MASK 0xffffffff > #define RLC_GPM_INT_DISABLE_TH0__DISABLE__SHIFT 0x0 > #define RLC_GPM_INT_DISABLE_TH1__DISABLE_MASK 0xffffffff > @@ -9126,14 +9122,8 @@ > #define RLC_SRM_DEBUG_SELECT__RESERVED__SHIFT 0x8 > #define RLC_SRM_DEBUG__DATA_MASK 0xffffffff > #define RLC_SRM_DEBUG__DATA__SHIFT 0x0 > -#define RLC_SRM_ARAM_ADDR__ADDR_MASK 0x3ff > -#define RLC_SRM_ARAM_ADDR__ADDR__SHIFT 0x0 > -#define RLC_SRM_ARAM_ADDR__RESERVED_MASK 0xfffffc00 > -#define RLC_SRM_ARAM_ADDR__RESERVED__SHIFT 0xa > #define RLC_SRM_ARAM_DATA__DATA_MASK 0xffffffff > #define RLC_SRM_ARAM_DATA__DATA__SHIFT 0x0 > -#define RLC_SRM_DRAM_ADDR__ADDR_MASK 0x3ff > -#define RLC_SRM_DRAM_ADDR__ADDR__SHIFT 0x0 > #define RLC_SRM_DRAM_ADDR__RESERVED_MASK 0xfffffc00 > #define RLC_SRM_DRAM_ADDR__RESERVED__SHIFT 0xa > #define RLC_SRM_DRAM_DATA__DATA_MASK 0xffffffff > @@ -17948,8 +17938,6 @@ > #define VGT_TESS_DISTRIBUTION__ACCUM_TRI__SHIFT 0x8 > #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD_MASK 0xff0000 > #define VGT_TESS_DISTRIBUTION__ACCUM_QUAD__SHIFT 0x10 > -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT_MASK 0xff000000 > -#define VGT_TESS_DISTRIBUTION__DONUT_SPLIT__SHIFT 0x18 > #define VGT_TF_RING_SIZE__SIZE_MASK 0xffff > #define VGT_TF_RING_SIZE__SIZE__SHIFT 0x0 > #define VGT_SYS_CONFIG__DUAL_CORE_EN_MASK 0x1 > @@ -20504,8 +20492,6 @@ > #define DIDT_SQ_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 > #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 > #define DIDT_SQ_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 > -#define DIDT_SQ_CTRL0__UNUSED_0_MASK 0xffffffc0 > -#define DIDT_SQ_CTRL0__UNUSED_0__SHIFT 0x6 > #define DIDT_SQ_CTRL1__MIN_POWER_MASK 0xffff > #define DIDT_SQ_CTRL1__MIN_POWER__SHIFT 0x0 > #define DIDT_SQ_CTRL1__MAX_POWER_MASK 0xffff0000 > @@ -20560,8 +20546,6 @@ > #define DIDT_DB_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 > #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 > #define DIDT_DB_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 > -#define DIDT_DB_CTRL0__UNUSED_0_MASK 0xffffffc0 > -#define DIDT_DB_CTRL0__UNUSED_0__SHIFT 0x6 > #define DIDT_DB_CTRL1__MIN_POWER_MASK 0xffff > #define DIDT_DB_CTRL1__MIN_POWER__SHIFT 0x0 > #define DIDT_DB_CTRL1__MAX_POWER_MASK 0xffff0000 > @@ -20616,8 +20600,6 @@ > #define DIDT_TD_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 > #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 > #define DIDT_TD_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 > -#define DIDT_TD_CTRL0__UNUSED_0_MASK 0xffffffc0 > -#define DIDT_TD_CTRL0__UNUSED_0__SHIFT 0x6 > #define DIDT_TD_CTRL1__MIN_POWER_MASK 0xffff > #define DIDT_TD_CTRL1__MIN_POWER__SHIFT 0x0 > #define DIDT_TD_CTRL1__MAX_POWER_MASK 0xffff0000 > @@ -20672,8 +20654,6 @@ > #define DIDT_TCP_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 > #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 > #define DIDT_TCP_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 > -#define DIDT_TCP_CTRL0__UNUSED_0_MASK 0xffffffc0 > -#define DIDT_TCP_CTRL0__UNUSED_0__SHIFT 0x6 > #define DIDT_TCP_CTRL1__MIN_POWER_MASK 0xffff > #define DIDT_TCP_CTRL1__MIN_POWER__SHIFT 0x0 > #define DIDT_TCP_CTRL1__MAX_POWER_MASK 0xffff0000 > @@ -20728,8 +20708,6 @@ > #define DIDT_DBR_CTRL0__DIDT_CTRL_RST__SHIFT 0x4 > #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE_MASK 0x20 > #define DIDT_DBR_CTRL0__DIDT_CLK_EN_OVERRIDE__SHIFT 0x5 > -#define DIDT_DBR_CTRL0__UNUSED_0_MASK 0xffffffc0 > -#define DIDT_DBR_CTRL0__UNUSED_0__SHIFT 0x6 > #define DIDT_DBR_CTRL1__MIN_POWER_MASK 0xffff > #define DIDT_DBR_CTRL1__MIN_POWER__SHIFT 0x0 > #define DIDT_DBR_CTRL1__MAX_POWER_MASK 0xffff0000 > -- > 1.9.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx
