Re: [PATCH v4 2/2] soundwire: qcom: add support for SoundWire controller

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On 11/1/19 12:22 PM, Srinivas Kandagatla wrote:


On 01/11/2019 16:39, Pierre-Louis Bossart wrote:

+static int qcom_swrm_prepare(struct snd_pcm_substream *substream,
+                 struct snd_soc_dai *dai)
+{
+    struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dai->dev);
+
+    if (!ctrl->sruntime[dai->id])
+        return -EINVAL;
+
+    return sdw_enable_stream(ctrl->sruntime[dai->id]);

So in hw_params you call sdw_prepare_stream() and in _prepare you call sdw_enable_stream()?

Shouldn't this be handled in a .trigger operation as per the documentation "From ASoC DPCM framework, this stream state is linked to
.trigger() start operation."

If I move sdw_enable/disable_stream() to trigger I get a big click noise on my speakers at start and end of every playback. Tried different things but nothing helped so far!. Enabling Speaker DACs only after SoundWire ports are enabled is working for me! There is nothing complicated on WSA881x codec side all the DACs are enabled/disabled as part of DAPM.

that looks like a work-around to me? If you do a bank switch without anything triggered, you are most likely sending a bunch of zeroes to your amplifier and enabling click/pop removals somehow.

It'd be worth looking into this, maybe there's a missing digital mute/unmute that's not done in the right order?

Digital mute does not help too, as they get unmuted before sdw_enable_stream() call in trigger, I hit same click sound.

Same in the disable path too!

Also I noticed that there are more than 20+ register read/writes in the sdw_enable_stream() path which took atleast 30 to 40 milliseconds.

wow, that's a very slow command bandwith, is this because of a low frame rate or the SLIMbus transport in the middle?

At any rate, we've got to improve the bank switch. The intent of the alternate banks is that software mirrors the register settings in the background and only updates what needs to be changed during the enable/disable part. when you operate with a fixed clock frequency usually it's only the channel enable that changes so it could be very fast (1 write deferred to the SSP point).

On the intel side our command bandwidth is comparable with the usual I2C/HDaudio codecs, but still things complicated and slower than they should be. I have been chasing a bug happening on bank switches in multi-stream configurations for 10+ days and it's quite hard to debug at the moment.

One possibility is to use regmap for the banked registers, and a manual mirroring after each bank switch. Or maybe we could even have an extension of regmap to do this for us.

I will try my luck checking the docs to see if I can find something which talks about this.


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