Re: [PATCH v4 3/7] ASoC: tegra: i2s: Add support for more than 2 channels

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

 



On 08/10/2019 16:29, Dmitry Osipenko wrote:
Hello Ben,

07.10.2019 18:31, Ben Dooks пишет:
From: Edward Cragg <edward.cragg@xxxxxxxxxxxxxxx>

The CIF configuration and clock setting is currently hard coded for 2
channels. Since the hardware is capable of supporting 1-8 channels add
support for reading the channel count from the supplied parameters to
allow for better TDM support. It seems the original implementation of this
driver was fixed at 2 channels for simplicity, and not implementing TDM.

Signed-off-by: Edward Cragg <edward.cragg@xxxxxxxxxxxxxxx>
[ben.dooks@xxxxxxxxxxxxxxx: added is_tdm and channel nr check]
[ben.dooks@xxxxxxxxxxxxxxx: merge edge control into set-format]
[ben.dooks@xxxxxxxxxxxxxxx: removed is_tdm and moved edge to hw_params]
Signed-off-by: Ben Dooks <ben.dooks@xxxxxxxxxxxxxxx>
---
  sound/soc/tegra/tegra30_i2s.c | 21 +++++++++++++--------
  1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/sound/soc/tegra/tegra30_i2s.c b/sound/soc/tegra/tegra30_i2s.c
index 063f34c882af..7382f7949bf4 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -67,6 +67,7 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
  {
  	struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
  	unsigned int mask = 0, val = 0;
+	unsigned int ch_mask, ch_val = 0;
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  	case SND_SOC_DAIFMT_NB_NF:
@@ -75,6 +76,7 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
  		return -EINVAL;
  	}
+ ch_mask = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_MASK;
  	mask |= TEGRA30_I2S_CTRL_MASTER_ENABLE;
  	switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  	case SND_SOC_DAIFMT_CBS_CFS:
@@ -90,10 +92,12 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai *dai,
  		TEGRA30_I2S_CTRL_LRCK_MASK;
  	switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  	case SND_SOC_DAIFMT_DSP_A:
+		ch_val = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;
  		val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
  		val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
  		break;
  	case SND_SOC_DAIFMT_DSP_B:
+		ch_val = TEGRA30_I2S_CH_CTRL_EGDE_CTRL_NEG_EDGE;

Downstream code sets DSP_B to POS_EDGE, looks like you have a typo here.
Or does DSP_B happen to work with the NEG_EDGE?

ok, will change, we've only been using SND_SOC_DAIFMT_DSP_A

For reference, is there a git repo with this version of tegra tdm support?


--
Ben Dooks				http://www.codethink.co.uk/
Senior Engineer				Codethink - Providing Genius

https://www.codethink.co.uk/privacy.html
_______________________________________________
Alsa-devel mailing list
Alsa-devel@xxxxxxxxxxxxxxxx
https://mailman.alsa-project.org/mailman/listinfo/alsa-devel




[Index of Archives]     [ALSA User]     [Linux Audio Users]     [Pulse Audio]     [Kernel Archive]     [Asterisk PBX]     [Photo Sharing]     [Linux Sound]     [Video 4 Linux]     [Gimp]     [Yosemite News]

  Powered by Linux