From: Edward Cragg <edward.cragg@xxxxxxxxxxxxxxx>
The CIF configuration and clock setting is currently hard coded for 2
channels. Since the hardware is capable of supporting 1-8 channels add
support for reading the channel count from the supplied parameters to
allow for better TDM support. It seems the original implementation of
this
driver was fixed at 2 channels for simplicity, and not implementing
TDM.
Signed-off-by: Edward Cragg <edward.cragg@xxxxxxxxxxxxxxx>
[ben.dooks@xxxxxxxxxxxxxxx: added is_tdm and channel nr check]
---
sound/soc/tegra/tegra30_i2s.c | 21 +++++++++++++--------
sound/soc/tegra/tegra30_i2s.h | 1 +
2 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/sound/soc/tegra/tegra30_i2s.c
b/sound/soc/tegra/tegra30_i2s.c
index b5372839f672..40bcc05a9dbb 100644
--- a/sound/soc/tegra/tegra30_i2s.c
+++ b/sound/soc/tegra/tegra30_i2s.c
@@ -86,14 +86,17 @@ static int tegra30_i2s_set_fmt(struct snd_soc_dai
*dai,
return -EINVAL;
}
+ i2s->is_tdm = false;
mask |= TEGRA30_I2S_CTRL_FRAME_FORMAT_MASK |
TEGRA30_I2S_CTRL_LRCK_MASK;
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_DSP_A:
+ i2s->is_tdm = true;
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
val |= TEGRA30_I2S_CTRL_LRCK_L_LOW;
break;
case SND_SOC_DAIFMT_DSP_B:
+ i2s->is_tdm = true;
val |= TEGRA30_I2S_CTRL_FRAME_FORMAT_FSYNC;
val |= TEGRA30_I2S_CTRL_LRCK_R_LOW;
break;
@@ -127,10 +130,13 @@ static int tegra30_i2s_hw_params(struct
snd_pcm_substream *substream,
struct device *dev = dai->dev;
struct tegra30_i2s *i2s = snd_soc_dai_get_drvdata(dai);
unsigned int mask, val, reg;
- int ret, sample_size, srate, i2sclock, bitcnt, audio_bits;
+ int ret, sample_size, srate, i2sclock, bitcnt, audio_bits, channels;
struct tegra30_ahub_cif_conf cif_conf;
- if (params_channels(params) != 2)
+ channels = params_channels(params);
+ if (channels > 8)
+ return -EINVAL;
+ if (channels != 2 && !i2s->is_tdm)
