On 31/07/2019 07:06, Marco Felsch wrote:
> Hi Thomas,
>
> again sorry for jumping in..
>
Np!
> On 19-07-30 18:26, Thomas Preston wrote:
>> On 30/07/2019 15:58, Mark Brown wrote:
>>> On Tue, Jul 30, 2019 at 01:09:36PM +0100, Thomas Preston wrote:
>>>> + case SND_SOC_BIAS_STANDBY:
>>>> + err = regulator_enable(tda7802->enable_reg);
>>>> + if (err < 0) {
>>>> + dev_err(component->dev, "Could not enable.\n");
>>>> + return err;
>>>> + }
>>>> + dev_dbg(component->dev, "Regulator enabled\n");
>>>> + msleep(ENABLE_DELAY_MS);
>>>
>>> Is this delay needed by the device or is it for the regulator to ramp?
>>> If it's for the regulator to ramp then the regulator should be doing it.
>>>
>>
>> According to the datasheet the device itself takes 10ms to rise from 0V
>> after PLLen is enabled. There are additional rise times but they are
>> negligible with default capacitor configuration (which we have).
>>
>> Good to know about the regulator rising configuration though. Thanks.
>
> Isn't it the regulator we mentioned to not use that because it is a
> GPIO?
>
Yeah it is - I intend to switch PLLen to gpio API.
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