On Sun, Jul 28, 2019 at 10:24:23PM +0300, Daniel Baluta wrote: > SAI IP supports up to 8 data lines. The configuration of > supported number of data lines is decided at SoC integration > time. > > This patch adds definitions for all related data TX/RX registers: > * TDR0..7, Transmit data register > * TFR0..7, Transmit FIFO register > * RDR0..7, Receive data register > * RFR0..7, Receive FIFO register > > Signed-off-by: Daniel Baluta <daniel.baluta@xxxxxxx> > --- > sound/soc/fsl/fsl_sai.c | 76 +++++++++++++++++++++++++++++++++++------ > sound/soc/fsl/fsl_sai.h | 36 ++++++++++++++++--- > 2 files changed, 98 insertions(+), 14 deletions(-) > > diff --git a/sound/soc/fsl/fsl_sai.c b/sound/soc/fsl/fsl_sai.c > index 6d3c6c8d50ce..17b0aff4ee8b 100644 > --- a/sound/soc/fsl/fsl_sai.c > +++ b/sound/soc/fsl/fsl_sai.c > @@ -704,7 +711,14 @@ static bool fsl_sai_readable_reg(struct device *dev, unsigned int reg) > case FSL_SAI_TCR3: > case FSL_SAI_TCR4: > case FSL_SAI_TCR5: > - case FSL_SAI_TFR: > + case FSL_SAI_TFR0: > + case FSL_SAI_TFR1: > + case FSL_SAI_TFR2: > + case FSL_SAI_TFR3: > + case FSL_SAI_TFR4: > + case FSL_SAI_TFR5: > + case FSL_SAI_TFR6: > + case FSL_SAI_TFR7: > case FSL_SAI_TMR: > case FSL_SAI_RCSR: > case FSL_SAI_RCR1: A tricky thing here is that those SAI instances on older SoC don't support multi data lines physically, while seemly having registers pre-defined. So your change doesn't sound doing anything wrong to them at all, I am still wondering if it is necessary to apply them to newer compatible only though, as for older compatibles of SAI, these registers would be useless and confusing if being exposed. What do you think? _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
