On Tue, Jul 23, 2019 at 01:54:15PM +0200, Michał Mirosław wrote: > On Tue, Jul 23, 2019 at 11:52:48AM +0100, Mark Brown wrote: > > Right, it's not like it's the same IP being dropped into multiple chips > > in an identical fashion. There's a lot of high level similarities in > > the register interfaces but also many small per device tweaks, and it's > > not clear what benefit we get from refactoring at this point. > This would be mainly code separation, so it's easier to understand and > has a potential for direct reuse. I can see that clock selection needs > to be changed, but the idea is to have it configurable via device-tree. Not all the world is DT... > I picked at random WM9081. It's FLL implementation looks very similar - > major diffferences being in FLL_OUTDIV selection (direct divider vs 2^N) > and register block offset. > Another random pick - WM8900. The general FLL idea seems the same, but > this one has a bit more complicated register layout, so I wouldn't > consider it at first. Yeah, there's a lot that on the surface looks similar but there's a lot of variations in the detail - different numbers getting plugged in, register layouts getting tweaked, different sets of sources and so on. I get that we can potentially combine the implementations which in theory is code reuse but what is the end goal for that code reuse given that all the refactoring is going to warrant some testing over a bunch of different parts.
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