Align the Intel IPC code with the recommended hardware sequences instead of confusing ones, remove useless command and clean-up interface definition. Daniel Baluta (1): ASoC: SOF: Do not send cmd via SHIM register Pierre-Louis Bossart (6): ASoC: SOF: Intel: cnl-ipc: read all IPC registers first ASoC: SOF: Intel: cnl-ipc: move code around for clarity ASoC: SOF: Intel: cnl-ipc: re-enable IPC IRQ at end of handler ASoC: SOF: Intel: hda-ipc: read all IPC registers first ASoC: SOF: Intel: hda-ipc: re-enable IPC IRQ at end of handler ASoC: SOF: Intel: ipc: don't check for HIPCCTL register value Slawomir Blauciak (1): ASoC: SOF: ipc: replace fw ready bitfield with explicit bit ordering include/sound/sof/info.h | 20 ++++++------- sound/soc/sof/intel/byt.c | 5 +--- sound/soc/sof/intel/cnl.c | 56 +++++++++++++++++------------------ sound/soc/sof/intel/hda-ipc.c | 43 +++++++++++++-------------- sound/soc/sof/ipc.c | 11 ++++--- 5 files changed, 67 insertions(+), 68 deletions(-) -- 2.20.1 _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
