Hi > > + /* > > + * Add fifo reset here, because the regcache_sync will > > + * write one more data to ETDR. > > + * Which will cause channel shift. > > Sounds like a bug to me...should fix it first by marking the data registers as > volatile. > The ETDR is a writable register, it is not volatile. Even we change it to Volatile, I don't think we can't avoid this issue. for the regcache_sync Just to write this register, it is correct behavior. Best regards Wang shengjiu _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx https://mailman.alsa-project.org/mailman/listinfo/alsa-devel
