From: Zhu Yingjiang <yingjiang.zhu@xxxxxxxxxxxxxxx>
By default, the I2S ports are configured in master mode during
DSP powerup sequences, the FS and BCLK lines will be driven on
startup, even when the topology file explicitly requires the
SSP to be slave.
This may be problematic for external components configured in
master mode who don't expect the Intel SOC/PCH to drive. Fix by
configuring the SSP as slave before the SSP outputs are enabled
to avoid this transient behavior.
When the topology file configures the SSP as clock master, the
initial slave configuration will be overridden.
Signed-off-by: Zhu Yingjiang <yingjiang.zhu@xxxxxxxxxxxxxxx>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@xxxxxxxxxxxxxxx>
---
sound/soc/sof/intel/hda-loader.c | 11 +++++++++++
sound/soc/sof/intel/hda.h | 6 ++++++
2 files changed, 17 insertions(+)
diff --git a/sound/soc/sof/intel/hda-loader.c b/sound/soc/sof/intel/hda-loader.c
index 6a44bc349e44..6427f0b3a2f1 100644
--- a/sound/soc/sof/intel/hda-loader.c
+++ b/sound/soc/sof/intel/hda-loader.c
@@ -84,6 +84,7 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
const struct sof_intel_dsp_desc *chip = hda->desc;
unsigned int status;
int ret;
+ int i;
/* step 1: power up corex */
ret = hda_dsp_core_power_up(sdev, chip->cores_mask);
@@ -92,6 +93,16 @@ static int cl_dsp_init(struct snd_sof_dev *sdev, const void *fwdata,
goto err;
}
+ /* DSP is powered up, set all SSPs to slave mode */
+ for (i = 0; i < chip->ssp_count; i++) {
+ snd_sof_dsp_update_bits_unlocked(sdev, HDA_DSP_BAR,
+ chip->ssp_base_offset
+ + i * SSP_DEV_MEM_SIZE
+ + SSP_SSC1_OFFSET,
+ SSP_SET_SLAVE,
+ SSP_SET_SLAVE);
+ }
+
/* step 2: purge FW request */
snd_sof_dsp_write(sdev, HDA_DSP_BAR, chip->ipc_req,
chip->ipc_req_mask | (HDA_DSP_IPC_PURGE_FW |
diff --git a/sound/soc/sof/intel/hda.h b/sound/soc/sof/intel/hda.h
index b2cf6fa15575..3799a3518106 100644
--- a/sound/soc/sof/intel/hda.h
+++ b/sound/soc/sof/intel/hda.h
@@ -349,6 +349,12 @@
#define APL_SSP_COUNT 6
#define CNL_SSP_COUNT 3
+/* SSP Registers */
+#define SSP_SSC1_OFFSET 0x4
+#define SSP_SET_SCLK_SLAVE BIT(25)
+#define SSP_SET_SFRM_SLAVE BIT(24)
+#define SSP_SET_SLAVE (SSP_SET_SCLK_SLAVE | SSP_SET_SFRM_SLAVE)
+
#define HDA_IDISP_CODEC(x) ((x) & BIT(2))
struct sof_intel_dsp_bdl {
--
2.17.1
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