On Sat, Dec 22, 2018 at 12:44:07AM +0800, Chen-Yu Tsai wrote: > On Fri, Dec 21, 2018 at 11:21 PM <codekipper@xxxxxxxxx> wrote: > > + regcache_cache_bypass(i2s->regmap, true); > > regmap_update_bits(i2s->regmap, SUN4I_I2S_FIFO_CTRL_REG, > > SUN4I_I2S_FIFO_CTRL_FLUSH_RX, > > SUN4I_I2S_FIFO_CTRL_FLUSH_RX); > > + regcache_cache_bypass(i2s->regmap, false); > IIRC the flush cache bit is self-clearing. So you likely want to mark > this register as volatile. If it is marked as volatile, then all access > to that register bypasses the cache, so the regcache_cache_bypass calls > are unneeded. Yes, that should be the case. > However, looking at the code, the write would seem to be ignored if the > regmap is in the cache_only state. We only set this when the bus clock > is disabled. Under such a condition, bypassing the cache and forcing a > write would be unwise, as the system either drops the write, or stalls > altogether. Right, access to a cache only register while the device is in cache only mode is not a great idea - the usual reason we're in cache only mode is that the device is in a state where I/O isn't going to work. One thing that can work for this if you need the register to be cached (but is a bit gross) is to do a write setting the self clearing bit then another immediately after resetting it back to the cleared state. That works OK for cases where the bit is a strobe and never retains state, though if the device isn't operational then needing to write to the register might indicate a bigger picture logic error (or it could be that the register map mixes random things into one register).
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