On Wed, May 30, 2018 at 10:35:25AM +0200, Daniel Mack wrote: > For instance, code for Zylonite does this: > /* Add 1 to the width for the leading clock cycle */ > pll_out = rate * (width + 1) * 8; > The commit which introduced these lines dates back to 2009 and was done by > you, Mark. Can you remember what the reason for this was? I've never seen > sample frames with 17 bits :) This is a setup that we can't generically > describe through .hw_params() or .dai_fmt() in the cpu dai, correct? I think it's copied from somewhere else probably, it looks like there's a bit of code motion going on. I bet it was just for I2S, keeping the extra clock cycle for the initial rising edge in the frame but not actually required. > So for both 22050 and 44100, the base frequency and all dividers are the > same, which can't be right. I assume these rates have never been used. I'll > ignore this and implement the table in the datasheet which should do the > right thing. Philipp? That looks buggy, yeah. I doubt anyone ever used 22.05kHz. > What we need, however, is a way to describe whether the dai is mclk master > or slave. Would we add a DT propery for that? That might be sensible, though the MCLK isn't really part of the DAI.
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