From: Pardha Saradhi K <pardha.saradhi.kesapragada@xxxxxxxxx>
As per HW recommendation, after clearing the RUN bit,
software must read a 0 from the RUN bit, before modifying
related control registers or re-starting the DMA engine.
Signed-off-by: Pardha Saradhi K <pardha.saradhi.kesapragada@xxxxxxxxx>
Signed-off-by: Sriram Periyasamy <sriramx.periyasamy@xxxxxxxxx>
---
sound/hda/hdac_stream.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/sound/hda/hdac_stream.c b/sound/hda/hdac_stream.c
index e1472c7ab6c1..2000ea6f48fa 100644
--- a/sound/hda/hdac_stream.c
+++ b/sound/hda/hdac_stream.c
@@ -70,8 +70,23 @@ EXPORT_SYMBOL_GPL(snd_hdac_stream_start);
*/
void snd_hdac_stream_clear(struct hdac_stream *azx_dev)
{
+ int timeout = 300;
+ unsigned char val;
+
snd_hdac_stream_updateb(azx_dev, SD_CTL,
SD_CTL_DMA_START | SD_INT_MASK, 0);
+
+ do {
+ udelay(3);
+ val = snd_hdac_stream_readb(azx_dev, SD_CTL) &
+ SD_CTL_DMA_START;
+ if (!val)
+ break;
+ } while (--timeout);
+
+ if (!timeout)
+ dev_err(azx_dev->bus->dev, "unable to stop the stream\n");
+
snd_hdac_stream_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
azx_dev->running = false;
}
--
2.7.4
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