Hi Nicolin, FYI, the error/warning still remains. tree: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git topic/fsl-ssi head: a5a86a7f87d7b684f0369e1f207bb294cfa58dde commit: a818aa5f967ba60522ee0ad181a0c5a96b65d999 [11/19] ASoC: fsl_ssi: Rename registers and fields macros config: arm-allmodconfig (attached as .config) compiler: arm-linux-gnueabi-gcc (Debian 7.2.0-11) 7.2.0 reproduce: wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross git checkout a818aa5f967ba60522ee0ad181a0c5a96b65d999 # save the attached .config to linux build tree make.cross ARCH=arm All warnings (new ones prefixed by >>): In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:87:0: warning: "SSI_SCR_TCH_EN" redefined #define SSI_SCR_TCH_EN 0x00000100 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:18:0: note: this is the location of the previous definition #define SSI_SCR_TCH_EN (1 << 8) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:88:0: warning: "SSI_SCR_SYS_CLK_EN" redefined #define SSI_SCR_SYS_CLK_EN 0x00000080 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:19:0: note: this is the location of the previous definition #define SSI_SCR_SYS_CLK_EN (1 << 7) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:92:0: warning: "SSI_SCR_I2S_MODE_SLAVE" redefined #define SSI_SCR_I2S_MODE_SLAVE 0x00000040 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:22:0: note: this is the location of the previous definition #define SSI_SCR_I2S_MODE_SLAVE (2 << 5) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:93:0: warning: "SSI_SCR_SYN" redefined #define SSI_SCR_SYN 0x00000010 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:24:0: note: this is the location of the previous definition #define SSI_SCR_SYN (1 << 4) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:94:0: warning: "SSI_SCR_NET" redefined #define SSI_SCR_NET 0x00000008 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:25:0: note: this is the location of the previous definition #define SSI_SCR_NET (1 << 3) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:95:0: warning: "SSI_SCR_RE" redefined #define SSI_SCR_RE 0x00000004 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:26:0: note: this is the location of the previous definition #define SSI_SCR_RE (1 << 2) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:96:0: warning: "SSI_SCR_TE" redefined #define SSI_SCR_TE 0x00000002 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:27:0: note: this is the location of the previous definition #define SSI_SCR_TE (1 << 1) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:97:0: warning: "SSI_SCR_SSIEN" redefined #define SSI_SCR_SSIEN 0x00000001 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:28:0: note: this is the location of the previous definition #define SSI_SCR_SSIEN (1 << 0) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:102:0: warning: "SSI_SISR_CMDAU" redefined #define SSI_SISR_CMDAU 0x00040000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:32:0: note: this is the location of the previous definition #define SSI_SISR_CMDAU (1 << 18) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:103:0: warning: "SSI_SISR_CMDDU" redefined #define SSI_SISR_CMDDU 0x00020000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:33:0: note: this is the location of the previous definition #define SSI_SISR_CMDDU (1 << 17) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:104:0: warning: "SSI_SISR_RXT" redefined #define SSI_SISR_RXT 0x00010000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:34:0: note: this is the location of the previous definition #define SSI_SISR_RXT (1 << 16) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:105:0: warning: "SSI_SISR_RDR1" redefined #define SSI_SISR_RDR1 0x00008000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:35:0: note: this is the location of the previous definition #define SSI_SISR_RDR1 (1 << 15) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:106:0: warning: "SSI_SISR_RDR0" redefined #define SSI_SISR_RDR0 0x00004000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:36:0: note: this is the location of the previous definition #define SSI_SISR_RDR0 (1 << 14) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:107:0: warning: "SSI_SISR_TDE1" redefined #define SSI_SISR_TDE1 0x00002000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:37:0: note: this is the location of the previous definition #define SSI_SISR_TDE1 (1 << 13) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:108:0: warning: "SSI_SISR_TDE0" redefined #define SSI_SISR_TDE0 0x00001000 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:38:0: note: this is the location of the previous definition #define SSI_SISR_TDE0 (1 << 12) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:109:0: warning: "SSI_SISR_ROE1" redefined #define SSI_SISR_ROE1 0x00000800 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:39:0: note: this is the location of the previous definition #define SSI_SISR_ROE1 (1 << 11) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:110:0: warning: "SSI_SISR_ROE0" redefined #define SSI_SISR_ROE0 0x00000400 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:40:0: note: this is the location of the previous definition #define SSI_SISR_ROE0 (1 << 10) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:111:0: warning: "SSI_SISR_TUE1" redefined #define SSI_SISR_TUE1 0x00000200 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:41:0: note: this is the location of the previous definition #define SSI_SISR_TUE1 (1 << 9) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:112:0: warning: "SSI_SISR_TUE0" redefined #define SSI_SISR_TUE0 0x00000100 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:42:0: note: this is the location of the previous definition #define SSI_SISR_TUE0 (1 << 8) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: >> sound/soc/fsl/fsl_ssi.h:113:0: warning: "SSI_SISR_TFS" redefined #define SSI_SISR_TFS 0x00000080 In file included from sound/soc/fsl/eukrea-tlv320.c:31:0: sound/soc/fsl/imx-ssi.h:43:0: note: this is the location of the previous definition #define SSI_SISR_TFS (1 << 7) In file included from sound/soc/fsl/eukrea-tlv320.c:32:0: vim +/SSI_SCR_TCH_EN +87 sound/soc/fsl/fsl_ssi.h 82 83 /* SSI Control Register -- REG_SSI_SCR 0x10 */ 84 #define SSI_SCR_SYNC_TX_FS 0x00001000 85 #define SSI_SCR_RFR_CLK_DIS 0x00000800 86 #define SSI_SCR_TFR_CLK_DIS 0x00000400 > 87 #define SSI_SCR_TCH_EN 0x00000100 > 88 #define SSI_SCR_SYS_CLK_EN 0x00000080 89 #define SSI_SCR_I2S_MODE_MASK 0x00000060 90 #define SSI_SCR_I2S_MODE_NORMAL 0x00000000 91 #define SSI_SCR_I2S_MODE_MASTER 0x00000020 > 92 #define SSI_SCR_I2S_MODE_SLAVE 0x00000040 > 93 #define SSI_SCR_SYN 0x00000010 > 94 #define SSI_SCR_NET 0x00000008 > 95 #define SSI_SCR_RE 0x00000004 > 96 #define SSI_SCR_TE 0x00000002 > 97 #define SSI_SCR_SSIEN 0x00000001 98 99 /* SSI Interrupt Status Register -- REG_SSI_SISR 0x14 */ 100 #define SSI_SISR_RFRC 0x01000000 101 #define SSI_SISR_TFRC 0x00800000 > 102 #define SSI_SISR_CMDAU 0x00040000 > 103 #define SSI_SISR_CMDDU 0x00020000 > 104 #define SSI_SISR_RXT 0x00010000 > 105 #define SSI_SISR_RDR1 0x00008000 > 106 #define SSI_SISR_RDR0 0x00004000 > 107 #define SSI_SISR_TDE1 0x00002000 > 108 #define SSI_SISR_TDE0 0x00001000 > 109 #define SSI_SISR_ROE1 0x00000800 > 110 #define SSI_SISR_ROE0 0x00000400 > 111 #define SSI_SISR_TUE1 0x00000200 > 112 #define SSI_SISR_TUE0 0x00000100 > 113 #define SSI_SISR_TFS 0x00000080 > 114 #define SSI_SISR_RFS 0x00000040 > 115 #define SSI_SISR_TLS 0x00000020 > 116 #define SSI_SISR_RLS 0x00000010 > 117 #define SSI_SISR_RFF1 0x00000008 > 118 #define SSI_SISR_RFF0 0x00000004 > 119 #define SSI_SISR_TFE1 0x00000002 > 120 #define SSI_SISR_TFE0 0x00000001 121 122 /* SSI Interrupt Enable Register -- REG_SSI_SIER 0x18 */ 123 #define SSI_SIER_RFRC_EN 0x01000000 124 #define SSI_SIER_TFRC_EN 0x00800000 > 125 #define SSI_SIER_RDMAE 0x00400000 > 126 #define SSI_SIER_RIE 0x00200000 > 127 #define SSI_SIER_TDMAE 0x00100000 > 128 #define SSI_SIER_TIE 0x00080000 > 129 #define SSI_SIER_CMDAU_EN 0x00040000 > 130 #define SSI_SIER_CMDDU_EN 0x00020000 > 131 #define SSI_SIER_RXT_EN 0x00010000 > 132 #define SSI_SIER_RDR1_EN 0x00008000 > 133 #define SSI_SIER_RDR0_EN 0x00004000 > 134 #define SSI_SIER_TDE1_EN 0x00002000 > 135 #define SSI_SIER_TDE0_EN 0x00001000 > 136 #define SSI_SIER_ROE1_EN 0x00000800 > 137 #define SSI_SIER_ROE0_EN 0x00000400 > 138 #define SSI_SIER_TUE1_EN 0x00000200 > 139 #define SSI_SIER_TUE0_EN 0x00000100 > 140 #define SSI_SIER_TFS_EN 0x00000080 > 141 #define SSI_SIER_RFS_EN 0x00000040 > 142 #define SSI_SIER_TLS_EN 0x00000020 > 143 #define SSI_SIER_RLS_EN 0x00000010 > 144 #define SSI_SIER_RFF1_EN 0x00000008 > 145 #define SSI_SIER_RFF0_EN 0x00000004 > 146 #define SSI_SIER_TFE1_EN 0x00000002 > 147 #define SSI_SIER_TFE0_EN 0x00000001 148 149 /* SSI Transmit Configuration Register -- REG_SSI_STCR 0x1C */ > 150 #define SSI_STCR_TXBIT0 0x00000200 > 151 #define SSI_STCR_TFEN1 0x00000100 > 152 #define SSI_STCR_TFEN0 0x00000080 > 153 #define SSI_STCR_TFDIR 0x00000040 > 154 #define SSI_STCR_TXDIR 0x00000020 > 155 #define SSI_STCR_TSHFD 0x00000010 > 156 #define SSI_STCR_TSCKP 0x00000008 > 157 #define SSI_STCR_TFSI 0x00000004 > 158 #define SSI_STCR_TFSL 0x00000002 > 159 #define SSI_STCR_TEFS 0x00000001 160 161 /* SSI Receive Configuration Register -- REG_SSI_SRCR 0x20 */ 162 #define SSI_SRCR_RXEXT 0x00000400 > 163 #define SSI_SRCR_RXBIT0 0x00000200 > 164 #define SSI_SRCR_RFEN1 0x00000100 > 165 #define SSI_SRCR_RFEN0 0x00000080 > 166 #define SSI_SRCR_RFDIR 0x00000040 > 167 #define SSI_SRCR_RXDIR 0x00000020 > 168 #define SSI_SRCR_RSHFD 0x00000010 > 169 #define SSI_SRCR_RSCKP 0x00000008 > 170 #define SSI_SRCR_RFSI 0x00000004 > 171 #define SSI_SRCR_RFSL 0x00000002 > 172 #define SSI_SRCR_REFS 0x00000001 173 174 /* 175 * SSI Transmit Clock Control Register -- REG_SSI_STCCR 0x24 176 * SSI Receive Clock Control Register -- REG_SSI_SRCCR 0x28 177 */ 178 #define SSI_SxCCR_DIV2_SHIFT 18 179 #define SSI_SxCCR_DIV2 0x00040000 180 #define SSI_SxCCR_PSR_SHIFT 17 181 #define SSI_SxCCR_PSR 0x00020000 182 #define SSI_SxCCR_WL_SHIFT 13 183 #define SSI_SxCCR_WL_MASK 0x0001E000 184 #define SSI_SxCCR_WL(x) \ 185 (((((x) / 2) - 1) << SSI_SxCCR_WL_SHIFT) & SSI_SxCCR_WL_MASK) 186 #define SSI_SxCCR_DC_SHIFT 8 187 #define SSI_SxCCR_DC_MASK 0x00001F00 188 #define SSI_SxCCR_DC(x) \ 189 ((((x) - 1) << SSI_SxCCR_DC_SHIFT) & SSI_SxCCR_DC_MASK) 190 #define SSI_SxCCR_PM_SHIFT 0 191 #define SSI_SxCCR_PM_MASK 0x000000FF 192 #define SSI_SxCCR_PM(x) \ 193 ((((x) - 1) << SSI_SxCCR_PM_SHIFT) & SSI_SxCCR_PM_MASK) 194 195 /* 196 * SSI FIFO Control/Status Register -- REG_SSI_SFCSR 0x2c 197 * 198 * Tx or Rx FIFO Counter -- SSI_SFCSR_xFCNTy Read-Only 199 * Tx or Rx FIFO Watermarks -- SSI_SFCSR_xFWMy Read/Write 200 */ 201 #define SSI_SFCSR_RFCNT1_SHIFT 28 202 #define SSI_SFCSR_RFCNT1_MASK 0xF0000000 > 203 #define SSI_SFCSR_RFCNT1(x) \ 204 (((x) & SSI_SFCSR_RFCNT1_MASK) >> SSI_SFCSR_RFCNT1_SHIFT) 205 #define SSI_SFCSR_TFCNT1_SHIFT 24 206 #define SSI_SFCSR_TFCNT1_MASK 0x0F000000 > 207 #define SSI_SFCSR_TFCNT1(x) \ 208 (((x) & SSI_SFCSR_TFCNT1_MASK) >> SSI_SFCSR_TFCNT1_SHIFT) 209 #define SSI_SFCSR_RFWM1_SHIFT 20 210 #define SSI_SFCSR_RFWM1_MASK 0x00F00000 > 211 #define SSI_SFCSR_RFWM1(x) \ 212 (((x) << SSI_SFCSR_RFWM1_SHIFT) & SSI_SFCSR_RFWM1_MASK) 213 #define SSI_SFCSR_TFWM1_SHIFT 16 214 #define SSI_SFCSR_TFWM1_MASK 0x000F0000 > 215 #define SSI_SFCSR_TFWM1(x) \ 216 (((x) << SSI_SFCSR_TFWM1_SHIFT) & SSI_SFCSR_TFWM1_MASK) 217 #define SSI_SFCSR_RFCNT0_SHIFT 12 218 #define SSI_SFCSR_RFCNT0_MASK 0x0000F000 > 219 #define SSI_SFCSR_RFCNT0(x) \ 220 (((x) & SSI_SFCSR_RFCNT0_MASK) >> SSI_SFCSR_RFCNT0_SHIFT) 221 #define SSI_SFCSR_TFCNT0_SHIFT 8 222 #define SSI_SFCSR_TFCNT0_MASK 0x00000F00 > 223 #define SSI_SFCSR_TFCNT0(x) \ 224 (((x) & SSI_SFCSR_TFCNT0_MASK) >> SSI_SFCSR_TFCNT0_SHIFT) 225 #define SSI_SFCSR_RFWM0_SHIFT 4 > 226 #define SSI_SFCSR_RFWM0_MASK 0x000000F0 > 227 #define SSI_SFCSR_RFWM0(x) \ 228 (((x) << SSI_SFCSR_RFWM0_SHIFT) & SSI_SFCSR_RFWM0_MASK) 229 #define SSI_SFCSR_TFWM0_SHIFT 0 > 230 #define SSI_SFCSR_TFWM0_MASK 0x0000000F > 231 #define SSI_SFCSR_TFWM0(x) \ 232 (((x) << SSI_SFCSR_TFWM0_SHIFT) & SSI_SFCSR_TFWM0_MASK) 233 234 /* SSI Test Register -- REG_SSI_STR 0x30 */ > 235 #define SSI_STR_TEST 0x00008000 > 236 #define SSI_STR_RCK2TCK 0x00004000 > 237 #define SSI_STR_RFS2TFS 0x00002000 > 238 #define SSI_STR_RXSTATE(x) (((x) >> 8) & 0x1F) > 239 #define SSI_STR_TXD2RXD 0x00000080 > 240 #define SSI_STR_TCK2RCK 0x00000040 > 241 #define SSI_STR_TFS2RFS 0x00000020 > 242 #define SSI_STR_TXSTATE(x) ((x) & 0x1F) 243 244 /* SSI Option Register -- REG_SSI_SOR 0x34 */ > 245 #define SSI_SOR_CLKOFF 0x00000040 > 246 #define SSI_SOR_RX_CLR 0x00000020 > 247 #define SSI_SOR_TX_CLR 0x00000010 > 248 #define SSI_SOR_INIT 0x00000008 249 #define SSI_SOR_WAIT_SHIFT 1 > 250 #define SSI_SOR_WAIT_MASK 0x00000006 > 251 #define SSI_SOR_WAIT(x) (((x) & 3) << SSI_SOR_WAIT_SHIFT) > 252 #define SSI_SOR_SYNRST 0x00000001 253 254 /* SSI AC97 Control Register -- REG_SSI_SACNT 0x38 */ 255 #define SSI_SACNT_FRDIV(x) (((x) & 0x3f) << 5) > 256 #define SSI_SACNT_WR 0x00000010 > 257 #define SSI_SACNT_RD 0x00000008 258 #define SSI_SACNT_RDWR_MASK 0x00000018 > 259 #define SSI_SACNT_TIF 0x00000004 > 260 #define SSI_SACNT_FV 0x00000002 > 261 #define SSI_SACNT_AC97EN 0x00000001 262 263 --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation
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