On 27/03/17 21:01, Mark Brown wrote:
On Sat, Mar 25, 2017 at 04:45:46PM +1100, Matt Flax wrote:
On 25/03/17 06:09, Mark Brown wrote:
Could you please be concrete about what the two formats you're talking
about here are and how these differences are observable on the wire? I
don't know what "two data word edge triggered ABP" means.
On the codec side it is a regular TDM stream.
On the SoC side, two channels are arbitrarily offset from a PCM frame sync
clock (PCM_FS) leading edge. I have chosen to have 64 bits per frame with 1
bit offset for the first word (from the leading edge) and 33 bits offset
(from the leading edge) for the second word. This resembles I2S, but it
doesn't have to for the bcm2835.
What's internal to the SoC is not relevant here, what matters is what's
externally visible. The formats on the DAI are how the SoC interfaces
with the outside world.
In this case, there is the TDM (DSP mode) protocol on the Codec. The SoC
however is communicating in channel pairs {{0, 1}, {2, 3}, {4, 5}, {6,
7}}. Each channel separated by the PCM_FS clk leading edge.
As far as the codec is concerned it is DSP mode. As far as the SoC is
concerned, it is not I2S, nor is it strictly DSP mode because there is
more then one PCM_FS per frame !
If we look at this from the perspective of the Codec, then it is DSP
mode. I am just not sure what to call the SoC's protocol, other then
multi-paired PCM.
Matt
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