Re: [PATCH 09/11] ASoC: Intel: Skylake: Fix DMA position reporting for capture stream

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 	 * HAD space reflects the actual data that is transferred.
 	 * Use the position buffer for capture, as DPIB write gets
 	 * completed earlier than the actual data written to the DDR.
+	 *
+	 * For capture stream following workaround is required to fix the
+	 * incorrect position reporting.
+	 *
+	 * 1. Wait for 20us before reading the DMA position in buffer once
+	 * the interrupt is generated for stream completion.

is this really 20us regardless of the sampling frequency/channel count?
20us is one sample at 48kHz so wondering how generic this work-around is...

Yes, this is independent of PCM parameters. Update happens on the
HDA frame boundary i.e. 20.833uSec.

Makes sense. it's worth updating the comments though to make it self-explanatory.

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