On Tue, Feb 07, 2017 at 10:09:36AM +1100, Matt Flax wrote:
> case SND_SOC_DAIFMT_CBS_CFM:
> clk_set_rate(dev->clk, sampling_rate * bclk_ratio);
> + case SND_SOC_DAIFMT_CBM_CFS:
Is this fall through deliberate?
> + /* Default data delay to 1 bit.
> + In I2S mode, we must have 2 channels */
> switch (dev->fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
> case SND_SOC_DAIFMT_I2S:
> + if (params_channels(params) != 2)
> + return -EINVAL;
> + case SND_SOC_DAIFMT_DSP_A:
> + case SND_SOC_DAIFMT_DSP_B:
> data_delay = 1;
> break;
> default:
Same here. This is also buggy in that it treats DSP A and DSP B
identically, they are different so the configuration must be incorrect
for one of them. I suspect this is configuring for DSP A.
You should also really have a setup() function that imposes a channel
constraint when in I2S mode, wm8988 is one example here.
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