On Thu, Jun 09, 2016 at 07:39:06PM +0200, Lars-Peter Clausen wrote: > Multiple devices from the ADAU family share the same PLL structure and > configuration register layout. Introduce a new helper module that can be > used to calculated the PLL configuration registers based on a specified > input frequency and the desired output frequency of the PLL. Sounds like we may be heading towards an MFD with a clock driver here?
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