On Fri, 03 Jun 2016 14:59:37 +0200,
jeeja.kp@xxxxxxxxx wrote:
>
> From: Dharageswari R <dharageswari.r@xxxxxxxxx>
>
> SW needs to set the PGCTL.LSRMD = 1 to disable LPSRAM retention
> feature,otherwise it may lead to SRAM ECC Errors.
Is this needed only for ASoC driver, or for SKL in general?
thanks,
Takashi
>
> Signed-off-by: Dharageswari R <dharageswari.r@xxxxxxxxx>
> Signed-off-by: Jeeja KP <jeeja.kp@xxxxxxxxx>
> Signed-off-by: Vinod Koul <vinod.koul@xxxxxxxxx>
> ---
> sound/soc/intel/skylake/skl.c | 3 +++
> sound/soc/intel/skylake/skl.h | 2 ++
> 2 files changed, 5 insertions(+)
>
> diff --git a/sound/soc/intel/skylake/skl.c b/sound/soc/intel/skylake/skl.c
> index 06d8c26..5a08826 100644
> --- a/sound/soc/intel/skylake/skl.c
> +++ b/sound/soc/intel/skylake/skl.c
> @@ -184,6 +184,7 @@ static int _skl_suspend(struct hdac_ext_bus *ebus)
> {
> struct skl *skl = ebus_to_skl(ebus);
> struct hdac_bus *bus = ebus_to_hbus(ebus);
> + struct pci_dev *pci = to_pci_dev(bus->dev);
> int ret;
>
> snd_hdac_ext_bus_link_power_down_all(ebus);
> @@ -193,6 +194,8 @@ static int _skl_suspend(struct hdac_ext_bus *ebus)
> return ret;
>
> snd_hdac_bus_stop_chip(bus);
> + update_pci_dword(pci, AZX_PCIREG_PGCTL,
> + AZX_PGCTL_LSRMD_MASK, AZX_PGCTL_LSRMD_MASK);
> skl_enable_miscbdcge(bus->dev, false);
> snd_hdac_bus_enter_link_reset(bus);
> skl_enable_miscbdcge(bus->dev, true);
> diff --git a/sound/soc/intel/skylake/skl.h b/sound/soc/intel/skylake/skl.h
> index 4b4b387..bd8db1d 100644
> --- a/sound/soc/intel/skylake/skl.h
> +++ b/sound/soc/intel/skylake/skl.h
> @@ -48,6 +48,8 @@
> #define AZX_REG_VS_SDXEFIFOS_XBASE 0x1094
> #define AZX_REG_VS_SDXEFIFOS_XINTERVAL 0x20
>
> +#define AZX_PCIREG_PGCTL 0x44
> +#define AZX_PGCTL_LSRMD_MASK (1 << 4)
> #define AZX_PCIREG_CGCTL 0x48
> #define AZX_CGCTL_MISCBDCGE_MASK (1 << 6)
>
> --
> 2.5.0
>
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