On Mon, 23 May 2016, Emmanuel Fusté wrote:
> /* pcm5102a in HW mode with external SCK (4wire mode)
> * at 128fs, 192fs or 256fs
> */
> pcm5102a-4w: pcm5102a {
> compatible = "simple-i2s-codec";
> rate = <SNDRV_PCM_RATE_8000_192000>;
> format = < SNDRV_PCM_FMTBIT_S16_LE
> |SNDRV_PCM_FMTBIT_S24_LE
> |SNDRV_PCM_FMTBIT_S32_LE>;
> };
> or
> /* pcm5102a in HW mode with PLL on BCK (3wire mode)
> * 16to384khz but only with bck rate of 64fs
> */
> pcm5102a-4w: pcm5102a {
> compatible = "simple-i2s-codec";
> rate = <SNDRV_PCM_RATE_8000_192000
> ^ SNDRV_PCM_RATE_8000>;
> format = <SNDRV_PCM_FMTBIT_S32_LE>;
> };
> Or
> /* ES9023 in asynchronous mode mclk > 37Mhz
> * I did not try bck rate <64fs as the sabre family did not generally
> * support it.
> */
> es9023: es9023 {
> compatible = "simple-i2s-codec";
> rate = <SNDRV_PCM_RATE_8000_192000>;
> format = <SNDRV_PCM_FMTBIT_S32_LE>;
> };
>
> We could use I2S friendly property instead of "format" :
> bckrates = <48, 64>;
>
>
> With two or tree more property (gpio for mute, de-emphasis and filter
> selection), you could cover 98% of I2S DAC with hardware only interfaces. It
> cover too startup mode of most hifi I2C or SPI controllable DAC. Which is a
> good starting point for chip for which a driver is not already written.
It seems to me that this only covers the cases where the is codec running
in slave mode with MCLK derived from the BCLK, but not cases where the
codec is master and needs to have its MCLK configured appropriately (in
terms of device-specifc clock source and PLL settings), or am I missing
something?
/Ricard
--
Ricard Wolf Wanderlöf ricardw(at)axis.com
Axis Communications AB, Lund, Sweden www.axis.com
Phone +46 46 272 2016 Fax +46 46 13 61 30
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