On 05/16/2016 01:07 PM, Ricard Wanderlof wrote:
>
> On Fri, 13 May 2016, Lars-Peter Clausen wrote:
>
>>> Having researched this further, it appears that commit
>>>
>>> 27d6e7d1c96c9f51379e0feb972fec26029098bc
>>>
>>> ASoC: adau17x1: Cache writes when core clock is disabled
>>
>> I think it is also related to commit 1c79771a7270 ("regmap: Use
>> regcache_mark_dirty() to indicate power loss or reset"). This changes the
>> regmap code to sync all registers under certain conditions.
>
> Yes, that commit seems to be the key, although I must admit that I can't
> get my head around the logic of that commit. The commit message says: "HW
> was not reset (maybe it was just clock-gated), so if we cached any writes,
> they should be sent to the hardware regardless of whether they match the
> HW default.". But if the device was indeed gated off, rather than reset,
> why should this make a difference when writing out the cache after gating
> the chip on again? If it were gated off and then on, doesn't this imply
> that the register settings won't change? Or is the idea that the chip
> might loose all its state while gated off and hence essentially needs to
> be reinitialized?
The register settings in the device will stay constant, but the cached
register settings might have changed. E.g. application changes the volume of
a control while the device is powered down. Since regmap does not (yet)
track which registers have changed it has to write out all of them.
>
> Regardless of the commit message, the code indeed does cause all the
> cached data to be written out when regcache_sync() is called in this case.
>
>> We still have the issue though that the CODEC is in an undefined state until
>> the first OFF to STANDBY transitions happens. Usually this will happen early
>> on when the CODEC is bound to the sound card, but if it is not bound
>> immediately it might stay there for a bit longer. So depending on the setup
>> this may or may not be a problem.
>
> So that means that in the probe function we should really write out the
> default values, by enabling SYSCLK_EN in the ADAU clock control register,
> and then calling regcache_sync() before disabling SYSCLK_EN again, and
> going to regcache_cache_only(..,true) ?
Sounds reasonable.
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