On Thu, May 12, 2016 at 08:48:54AM +0200, Petr Kulhavy wrote: > The clock calculation has several issues: > 1) if PLL is used in master mode the BCLK output runs at double the speed > 2) de-facto only 44.1kHz and 48kHz sampling rates are supported, other > rates like 8kHz, 12kHz, 24kHz fail to find the proper BCLK divider > 3) the wm8985->sysclk variable has a misleading name and is used wrongly > in the clock calculation in wm8985_hw_params() which is the root cause > for (1) > 4) wm8985->bclk is used only in wm8985_hw_params() and therefore no > need to store it in the wm8985_priv structure > > Therefore the clock calculation is rewritten in more clean and proper way: > - move wm8985_priv->bclk as a local variable into mw8985_hw_params() > - new variable wm8985_priv->pllout holds the actual frequency that is input > to the MCLKDIV post-divider > - move wm8985_priv->sysclk as a local variable into mw8985_hw_params() > - sysclk is now always calculated as 256 * fs > - the MCLKDIV is looked up as pllout/sysclk > - fs_ratios[] is replaced by simpler mclk_divs[] lookup table > > With this patch all rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1 and 48kHz > work properly and generate the correct BCLK. > > Signed-off-by: Petr Kulhavy <petr@xxxxxxxxx> > --- Reviewed-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxxxxxxxx> Thanks, Charles _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
