On Mon, Apr 25, 2016 at 3:36 PM, Caleb Crome <caleb@xxxxxxxxx> wrote: > The CCSR_SSI_SOR is a register that clears the TX and/or the RX fifo > on the i.MX SSI port. The fsl_ssi_trigger writes this register in > order to clear the fifo at trigger time. > > However, since the CCSR_SSI_SOR register is not in the volatile list, > the caching mechanism prevented the register write in the trigger > function. This caused the fifo to not be cleared (because the value > was unchanged from the last time the register was written), and thus > causes the channels in both TDM or simple I2S mode to slip and be in > the wrong time slots on SSI restart. > > This has gone unnoticed for so long because with simple stereo mode, > the consequence is that left and right are swapped, which isn't that > noticeable. However, it's catestrophic in some systems that > require the channels to be in the right slots. > > Signed-off-by: Caleb Crome <caleb@xxxxxxxxx> > Suggested-by: Arnaud Mouiche <arnaud.mouiche@xxxxxxxxxxx> Reviewed-by: Fabio Estevam <fabio.estevam@xxxxxxx> _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
