On Mon, Jan 18, 2016 at 7:26 AM, Arnaud Mouiche
<arnaud.mouiche@xxxxxxxxxxx> wrote:
>
> If the capture is already running while playback is started, it is highly
> probable (>80% in a 8 channels scenario) that samples are lost between
> the DMA and TX fifo.
>
> The reason is that SIER.TDMAE is set before STCR.TFEN0, leaving a time
> window where the FIFO doesn't receive the samples written by the DMA.
>
> This particular case happened only if capture is already enabled as
> SCR.SSIEN is already set at the playback startup instant.
>
> Signed-off-by: Arnaud Mouiche <arnaud.mouiche@xxxxxxxxxxx>
> ---
> sound/soc/fsl/fsl_ssi.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/sound/soc/fsl/fsl_ssi.c b/sound/soc/fsl/fsl_ssi.c
> index 13613fd..c9ba8ca 100644
> --- a/sound/soc/fsl/fsl_ssi.c
> +++ b/sound/soc/fsl/fsl_ssi.c
> @@ -488,9 +488,9 @@ static void fsl_ssi_config(struct fsl_ssi_private *ssi_private, bool enable,
> * (online configuration)
> */
> if (enable) {
> - regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
> regmap_update_bits(regs, CCSR_SSI_SRCR, vals->srcr, vals->srcr);
> regmap_update_bits(regs, CCSR_SSI_STCR, vals->stcr, vals->stcr);
> + regmap_update_bits(regs, CCSR_SSI_SIER, vals->sier, vals->sier);
> } else {
> u32 sier;
> u32 srcr;
> --
> 1.9.1
>
Tested-By: Caleb Crome <caleb@xxxxxxxxx>
Reviewed-"By: Caleb Crome <caleb@xxxxxxxxx>
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