On Tue, Mar 22, 2016 at 11:57:05AM +0800, John Hsu wrote: > @@ -1116,6 +1116,9 @@ static int nau8825_configure_sysclk(struct nau8825 *nau8825, int clk_id, > regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, > NAU8825_CLK_SRC_MASK, NAU8825_CLK_SRC_MCLK); > regmap_update_bits(regmap, NAU8825_REG_FLL6, NAU8825_DCO_EN, 0); > + /* MCLK not changed by clock tree */ > + regmap_update_bits(regmap, NAU8825_REG_CLK_DIVIDER, > + NAU8825_CLK_MCLK_SRC_MASK, 0); I'm going to apply this since I suspect there are already similar assumptions in the code but it does look like the issues Ben raised with one of your other patches with confusing sysclk management and overall device power might apply here. We can't rely on people changing the clock configuration in lower power modes.
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