On Fri, Feb 05, 2016 at 12:19:07PM +0530, Vinod Koul wrote: > From: "Dharageswari.R" <dharageswari.r@xxxxxxxxx> > > The SoC has MCLK output which is typically required by codecs. > The MCLK is controlled by DSP FW, so driver can configure that by > sending DMA_CONTROL IPC. The configuration for MCLK is present > in the endpoint blob. For integration with CODEC drivers this clock should really be exposed via the clock API too.
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