When switching between two clock sources using the FLL freerun to smooth the transition we should wait 32uS after putting the FLL into freerun before we proceed. In practice we appear to be getting enough delay from the surrounding code, but better to make it explicit. Signed-off-by: Charles Keepax <ckeepax@xxxxxxxxxxxxxxxxxxxxxxxxxxx> --- sound/soc/codecs/arizona.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/sound/soc/codecs/arizona.c b/sound/soc/codecs/arizona.c index e76ecc7..8cd448c 100644 --- a/sound/soc/codecs/arizona.c +++ b/sound/soc/codecs/arizona.c @@ -2215,6 +2215,7 @@ static int arizona_enable_fll(struct arizona_fll *fll) regmap_update_bits_async(fll->arizona->regmap, fll->base + 1, ARIZONA_FLL1_FREERUN, ARIZONA_FLL1_FREERUN); + udelay(32); } /* -- 1.7.2.5 _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
