Hi Returning back to this discussion that slipped away from my mailbox. On Fri, Aug 14, 2015 at 12:01 PM, Mark Brown <broonie@xxxxxxxxxx> wrote: > On Fri, Jul 17, 2015 at 10:38:56AM -0700, Anatol Pomozov wrote: >> According to the datasheet RESET is active low pin, i.e. system goes to reset >> state when pin is low. >> >> Handle logic state correctly - set reset_pin to logical 0 at boot time, and >> set it to logical 1 when we need to reset the chip. > > I'm a bit confused here - how was the original code (written by you it > seems...) tested? This looks like it's fixing the device being held in > reset when it should be operation which seems like something that'd get > noticed. Are there existing systems that the current code works for > which we need to handle here? While working with the original patch you mentioned I missed the active low description at RESET pin. I configured gpio in the dts as ACTIVE_HIGH and set the logic state to 0 at suspend mode. This puts the chip into reset state correctly. Later I discovered correct polarity and given change modifies gpio properties accordingly. I also changed our dts gpio to ACTIVE_LOW. Chip reset state still works as expected. The change does not modify anything at the signalling level, it just adds double negative to the code. Compare: pin configured as ACTIVE_HIGH - to move codec out of reset we need to set gpio logic level to 1. Physical signal is 1. pin configured as ACTIVE_LOW - to move codec out of reset we need to set gpio logic level to 0. Gpio becomes non-active that is represented by physical signal level 1. _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
