On Sat, Aug 14, 2010 at 4:35 AM, Mark Brown
<broonie@xxxxxxxxxxxxxxxxxxxxxxxxxxx> wrote:
> Implement set_sysclk() and then rather than assuming 256fs use the
> supplied value to calculate and configure the clock ratio for the
> currently used sample rate. As a side effect we also end up
> implementing clock selection for the ADC path.
>
> In order to avoid confusion remove the existing set_clkdiv() based
> configuration of the clock source for the DAC and update the SMDK64xx
> driver (which is the only in-tree user of the CODEC).
>
> Signed-off-by: Mark Brown <broonie@xxxxxxxxxxxxxxxxxxxxxxxxxxx>
> ---
> sound/soc/codecs/wm8580.c | 101 +++++++++++++++++++++++++++--------
> sound/soc/codecs/wm8580.h | 14 +++---
> sound/soc/s3c24xx/smdk64xx_wm8580.c | 9 ++--
> 3 files changed, 90 insertions(+), 34 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8580.c b/sound/soc/codecs/wm8580.c
> index 9964f02..3d7ff55 100644
> --- a/sound/soc/codecs/wm8580.c
> +++ b/sound/soc/codecs/wm8580.c
(snip)
> @@ -666,6 +672,55 @@ static int wm8580_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
> return 0;
> }
>
> +static int wm8580_set_sysclk(struct snd_soc_dai *dai, int clk_id,
> + unsigned int freq, int dir)
> +{
> + struct snd_soc_codec *codec = dai->codec;
> + struct wm8580_priv *wm8580 = snd_soc_codec_get_drvdata(codec);
> + int sel, sel_mask, sel_shift;
> +
> + switch (dai->driver->id) {
> + case WM8580_DAI_PAIFTX:
> + sel_mask = 0x3;
> + sel_shift = 0;
> + break;
> +
> + case WM8580_DAI_PAIFRX:
> + sel_mask = 0xc;
> + sel_shift = 3;
> + break;
These CLKSEL settings looks different with my WM8580 datasheet
(released March 2009, Rev 4.7).
I think these codes look...
+ case WM8580_DAI_PAIFRX:
+ sel_mask = 0x3;
+ sel_shift = 0;
+ break;
+
+ case WM8580_DAI_PAIFTX:
+ sel_mask = 0xc;
+ sel_shift = 2;
+ break;
> +
> + default:
> + BUG_ON("Unknown DAI driver ID\n");
> + return -EINVAL;
> + }
> +
> + switch (clk_id) {
> + case WM8580_CLKSRC_ADCMCLK:
> + if (dai->id != WM8580_DAI_PAIFTX)
> + return -EINVAL;
> + sel = 0 << sel_shift;
> + break;
During my test case with smdk6410 board, clock source of ADC should be
set by ADCMCLK, if we want to hear a correct sound on playback and
capture. And when ADC select MCLK or PLLA, source clock was broken
both of playback and capture.
Can you verify this(set source clock of ADC set to ADCMCLK) is right
or is there something missing on other settings?
> + case WM8580_CLKSRC_PLLA:
> + sel = 1 << sel_shift;
> + break;
> + case WM8580_CLKSRC_PLLB:
> + sel = 2 << sel_shift;
> + break;
> + case WM8580_CLKSRC_MCLK:
> + sel = 3 << sel_shift;
> + break;
> + default:
> + dev_err(codec->dev, "Unknown clock %d\n", clk_id);
> + return -EINVAL;
> + }
> +
(snip)
>
> --
> 1.7.1
>
> _______________________________________________
> Alsa-devel mailing list
> Alsa-devel@xxxxxxxxxxxxxxxx
> http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
>
Thanks,
Claude
_______________________________________________
Alsa-devel mailing list
Alsa-devel@xxxxxxxxxxxxxxxx
http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
