On Wed, 04 Nov 2009 19:46:49 +0000
Liam Girdwood <lrg@xxxxxxxxxxxxxxx> wrote:
> > > + /* calc best frame size for rate and clock divider */
> > > + do {
> > > + frame_size = (mcbsp_data->in_freq / div) / params_rate(params);
> > > + pr_debug("freq %d, rate %d, frame size %d, div %d\n",
> > > + mcbsp_data->in_freq, params_rate(params), frame_size, div);
> > > +
> > > + if (frame_size > 256)
> > > + div++;
> > > + } while (frame_size > 256);
> > > +
This would be better if it tries to calculate minimum frame size. Now
the algorithm stops when the frame_size is 256 and leads to higher
bit clock.
E.g. 4 * 16bits * 48 kHz and using 96 MHz internal clock:
Algorithm: div = 8, frame_size = 250 and bit clock = 12 MHz.
Possible dividers and frame_sizes:
25*80 (-> best, bit clock = 3.840 MHz)
20*100
16*125
10*200
8*250
> > This chunk changes the semantics of other devices which I have never tested.
> >
> > I also dont know how much damage it does if it does to slave mode. In fact
> > I think it might break it in cases which are actually allowable as it uses
> > the omap as its clock constraint and not the clock source.
> >
>
IRCC, the CLKGDV doesn't have effect while OMAP is slave but I can test
that with Beagle.
> Btw, this has been reworked to avoid all I2S paths since you last worked
> on it.
>
Probably that is not necessary if the algorithm above finds a frame
size (½ for dual-phase frames) which doesn't exceed I2S word size?
Uniform code is allways better :-)
--
Jarkko
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