Hi Peter, Thanks for the help. I don't believe it's possible for me to try the master/slave switch. Please take a look at http://www.efn.org/~rick/pub/wm8731.jpg Note that DACLRC and ADCLRC are connected. This requires me to run as slave, right? Our bit clock line is buffered so I don't think that will be a problem. Rick > > Yes, I had tried 8 before and just tried it now. Same result. It > > really seems like there is a DMA issue. Can you think of anything > > else to try before I dive into the DMA code? > > > Ok, that wasn't the reason. > > Have you tried to reverse roles of codec and omap? I.e. by using > the codec as a master and omap as a slave with SND_SOC_DAIFMT_CBM_CFM. > > I don't think there is any HW reason as you have seen the bit-clock and > frame sync signals toggling but I remember one case few years back > where codec had slight too high capacitive load on the bit-clock line. > That was then causing unstable frame sync as it was internally derived > directly from the bit-clock pin without any buffer. Bit-clock signal > looked just fine on oscilloscope but wasn't well enough for internal > circuits of the cpu. > > So if assuming similar problem here, I could imagine that if the FSX is > used similar way directly inside the omap and if signal is not well > enough, the McBSP and DMA may not be running. > > This migh be a bit far reason to look for but at least easy to try by > switching the roles as then the codec is driving the both bit-clock and > fs. > > _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
