On Fri, Jul 03, 2009 at 12:15:45PM +0200, Lars-Peter Clausen wrote: > Mark Brown wrote: > >Only 62 of the registers are cached - please see the register cache > >access code. > Yes. Thats the problem. The register cache holds place for 62 > elements where as there are 63 register which should be cached. > In the register cache access code you subtract one from the > registers index to get it's index in the register cache array, so > the last register has the index 62. Which means it is the 63th > element of the array and thus the array has to consist of 63 > elements. OK, that makes sense. I will apply your patch with a rewritten commit message which explains the issue - the problem is not that there is one less register in the cache than is in use, it's that there is one less register in the cache than is *cached*. As I say the code deliberately doesn't cache one of the registers. > >I'm not 100% sure what you mean here but I suspect you're misreading the > >register cache access code? > The register cache access code uses one-based indexing so the first Right, that makes sense with the above. _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
