Hi Peter,
Peter Ujfalusi wrote:
> On Wednesday 27 May 2009 16:07:23 ext Janusz Krzysztofik wrote:
>> static struct omap_mcbsp_reg_cfg mcbsp_regs = {
>> .spcr2 = FREE | XRST | GRST | XINTM(3) | FRST,
>> .spcr1 = RINTM(3) | RRST,
>> .rcr2 = RPHASE | RWDLEN2(OMAP_MCBSP_WORD_16) | RFRLEN2(0),
>> .rcr1 = RWDLEN1(OMAP_MCBSP_WORD_16) | RFRLEN1(0),
>> .xcr2 = XPHASE | XWDLEN2(OMAP_MCBSP_WORD_16) | XFRLEN2(0),
>> .xcr1 = XWDLEN1(OMAP_MCBSP_WORD_16) | XFRLEN1(0),
>> .srgr1 = CLKGDV(0),
>> .srgr2 = GSYNC,
>> };
>
> I wonder has this been working at all???
> FPER is not configured in srgr2 (actually it is 0, which means that the frame
> period is 1...)
> FWID is not configured in srgr1 (it is 0, which means the FS is a pulse,
> length is 1)
> Since CLKXP, CLKRP is 0, it suggests inverted bitclock.
> FSXP, FSRP is 0, so it must have normal FS polarity in DSP mode, or inverted
> polarity in I2S mode???
> Data delay is 0 for rx and tx.
>
> In all, I think this is a missconfigured DSP_B mode with inverted bitclock.
> Can you try this:
> err = snd_soc_dai_set_fmt(cpu_dai,
> SND_SOC_DAIFMT_DSP_B |
> SND_SOC_DAIFMT_IB_NF |
> SND_SOC_DAIFMT_CBM_CFM);
Already tried before, did not help.
>> So I will try the following then:
>> err = snd_soc_dai_set_fmt(cpu_dai,
>> SND_SOC_DAIFMT_DSP_B |
>> SND_SOC_DAIFMT_NB_IF |
>> SND_SOC_DAIFMT_CBM_CFM);
>> and this:
>> err = snd_soc_dai_set_fmt(cpu_dai,
>> SND_SOC_DAIFMT_DSP_A |
>> SND_SOC_DAIFMT_NB_IF |
>> SND_SOC_DAIFMT_CBM_CFM);
>> and give you a feedback.
Sorry, I did not answer since I gave up trying different dai format
settings after discovering that the original driver still worked with
register settings taken directly form its prototype osk board code.
Anyway, I think I'll have to get back here after DMA interrupts start
working.
Thanks,
Janusz
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