AC97 driver for mpc5200
I've implemented retries for when the AC97 hardware doesn't reset on
first try. About 10% of the time both the Efika and pcm030 AC97 codecs
don't reset on first try and need to be poked multiple times. Failure
is indicated by not having the link clock start ticking. Every once in
a while even five pokes won't get the link started and I have to power
cycle.
Signed-off-by: Jon Smirl <jonsmirl@xxxxxxxxx>
---
sound/soc/fsl/Kconfig | 11 +
sound/soc/fsl/Makefile | 1
sound/soc/fsl/mpc5200_psc_ac97.c | 392 ++++++++++++++++++++++++++++++++++++++
sound/soc/fsl/mpc5200_psc_ac97.h | 15 +
4 files changed, 419 insertions(+), 0 deletions(-)
create mode 100644 sound/soc/fsl/mpc5200_psc_ac97.c
create mode 100644 sound/soc/fsl/mpc5200_psc_ac97.h
diff --git a/sound/soc/fsl/Kconfig b/sound/soc/fsl/Kconfig
index 1918c78..3bce952 100644
--- a/sound/soc/fsl/Kconfig
+++ b/sound/soc/fsl/Kconfig
@@ -29,3 +29,14 @@ config SND_SOC_MPC5200_I2S
select PPC_BESTCOMM_GEN_BD
help
Say Y here to support the MPC5200 PSCs in I2S mode.
+
+config SND_SOC_MPC5200_AC97
+ tristate "Freescale MPC5200 PSC in AC97 mode driver"
+ depends on PPC_MPC52xx && PPC_BESTCOMM
+ select AC97_BUS
+ select SND_MPC52xx_DMA
+ select PPC_BESTCOMM_GEN_BD
+ help
+ Say Y here to support the MPC5200 PSCs in AC97 mode.
+
+
diff --git a/sound/soc/fsl/Makefile b/sound/soc/fsl/Makefile
index 7731ef2..14631a1 100644
--- a/sound/soc/fsl/Makefile
+++ b/sound/soc/fsl/Makefile
@@ -13,4 +13,5 @@ obj-$(CONFIG_SND_SOC_MPC8610) += snd-soc-fsl-ssi.o snd-soc-fsl-dma.o
# MPC5200 Platform Support
obj-$(CONFIG_SND_MPC52xx_DMA) += mpc5200_dma.o
obj-$(CONFIG_SND_SOC_MPC5200_I2S) += mpc5200_psc_i2s.o
+obj-$(CONFIG_SND_SOC_MPC5200_AC97) += mpc5200_psc_ac97.o
diff --git a/sound/soc/fsl/mpc5200_psc_ac97.c b/sound/soc/fsl/mpc5200_psc_ac97.c
new file mode 100644
index 0000000..480b677
--- /dev/null
+++ b/sound/soc/fsl/mpc5200_psc_ac97.c
@@ -0,0 +1,392 @@
+/*
+ * linux/sound/mpc5200-ac97.c -- AC97 support for the Freescale MPC52xx chip.
+ *
+ * Copyright (C) 2009 Jon Smirl, Digispeaker
+ * Author: Jon Smirl <jonsmirl@xxxxxxxxx>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/of_platform.h>
+
+#include <sound/pcm.h>
+#include <sound/pcm_params.h>
+#include <sound/soc.h>
+
+#include <asm/mpc52xx_psc.h>
+
+#include "mpc5200_dma.h"
+#include "mpc5200_psc_ac97.h"
+
+#define DRV_NAME "mpc5200-psc-ac97"
+
+/* ALSA only supports a single AC97 device so static is recommend here */
+static struct psc_dma *psc_dma;
+
+static unsigned short psc_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
+{
+ int timeout;
+ unsigned int val;
+
+ spin_lock(&psc_dma->lock);
+
+ /* Wait for it to be ready */
+ timeout = 1000;
+ while ((--timeout) && (in_be16(&psc_dma->psc_regs->sr_csr.status) &
+ MPC52xx_PSC_SR_CMDSEND))
+ udelay(10);
+
+ if (!timeout) {
+ pr_err("timeout on ac97 bus (rdy)\n");
+ return 0xffff;
+ }
+
+ /* Do the read */
+ out_be32(&psc_dma->psc_regs->ac97_cmd, (1<<31) | ((reg & 0x7f) << 24));
+
+ /* Wait for the answer */
+ timeout = 1000;
+ while ((--timeout) && !(in_be16(&psc_dma->psc_regs->sr_csr.status) &
+ MPC52xx_PSC_SR_DATA_VAL))
+ udelay(10);
+
+ if (!timeout) {
+ pr_err("timeout on ac97 read (val) %x\n",
+ in_be16(&psc_dma->psc_regs->sr_csr.status));
+ return 0xffff;
+ }
+
+ /* Get the data */
+ val = in_be32(&psc_dma->psc_regs->ac97_data);
+ if (((val>>24) & 0x7f) != reg) {
+ pr_err("reg echo error on ac97 read\n");
+ return 0xffff;
+ }
+ val = (val >> 8) & 0xffff;
+
+ spin_unlock(&psc_dma->lock);
+ return (unsigned short) val;
+}
+
+static void psc_ac97_write(struct snd_ac97 *ac97,
+ unsigned short reg, unsigned short val)
+{
+ int timeout;
+
+ spin_lock(&psc_dma->lock);
+
+ /* Wait for it to be ready */
+ timeout = 1000;
+ while ((--timeout) && (in_be16(&psc_dma->psc_regs->sr_csr.status) &
+ MPC52xx_PSC_SR_CMDSEND))
+ udelay(10);
+
+ if (!timeout) {
+ pr_err("timeout on ac97 write\n");
+ return;
+ }
+
+ /* Write data */
+ out_be32(&psc_dma->psc_regs->ac97_cmd,
+ ((reg & 0x7f) << 24) | (val << 8));
+
+ spin_unlock(&psc_dma->lock);
+}
+
+static void psc_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+ struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
+
+ out_be32(®s->sicr, psc_dma->sicr | MPC52xx_PSC_SICR_AWR);
+ udelay(3);
+ out_be32(®s->sicr, psc_dma->sicr);
+}
+
+static int psc_ac97_cold_reset_check(struct snd_ac97 *ac97)
+{
+ int max_reset, timeout;
+ struct mpc52xx_psc __iomem *regs = psc_dma->psc_regs;
+
+ /* AC97 clock is generated by the codec.
+ * Ensure that it starts ticking after codec reset.
+ */
+ for (max_reset = 0; max_reset < 5; max_reset++) {
+
+ /* Do a cold reset */
+ out_8(®s->op1, MPC52xx_PSC_OP_RES);
+ udelay(10);
+ out_8(®s->op0, MPC52xx_PSC_OP_RES);
+ udelay(50);
+
+ /* PSC recover from cold reset
+ * (cfr user manual, not sure if useful)
+ */
+ out_be32(®s->sicr, in_be32(®s->sicr));
+
+ psc_ac97_warm_reset(ac97);
+
+ /* first make sure AC97 clock is low */
+ for (timeout = 0; ((in_8(®s->ipcr_acr.ipcr) & 0x80) != 0) &&
+ (timeout < 100); timeout++)
+ udelay(10);
+ if (timeout == 100)
+ continue;
+
+ /* then wait for the transition to high */
+ for (timeout = 0; ((in_8(®s->ipcr_acr.ipcr) & 0x80) == 0) &&
+ (timeout < 100); timeout++)
+ udelay(10);
+ if (timeout == 100)
+ continue;
+
+ break;
+ }
+ if (max_reset == 5)
+ return -ENODEV;
+ return 0;
+}
+
+static void psc_ac97_cold_reset(struct snd_ac97 *ac97)
+{
+ psc_ac97_cold_reset_check(ac97);
+
+}
+
+struct snd_ac97_bus_ops soc_ac97_ops = {
+ .read = psc_ac97_read,
+ .write = psc_ac97_write,
+ .reset = psc_ac97_cold_reset,
+ .warm_reset = psc_ac97_warm_reset,
+};
+EXPORT_SYMBOL_GPL(soc_ac97_ops);
+
+static int psc_ac97_hw_analog_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct psc_dma *psc_dma = cpu_dai->private_data;
+
+ dev_dbg(psc_dma->dev, "%s(substream=%p) p_size=%i p_bytes=%i"
+ " periods=%i buffer_size=%i buffer_bytes=%i channels=%i"
+ " rate=%i format=%i\n",
+ __func__, substream, params_period_size(params),
+ params_period_bytes(params), params_periods(params),
+ params_buffer_size(params), params_buffer_bytes(params),
+ params_channels(params), params_rate(params),
+ params_format(params));
+
+
+ if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ if (params_channels(params) == 1)
+ psc_dma->slots |= 0x00000100;
+ else
+ psc_dma->slots |= 0x00000300;
+ } else {
+ if (params_channels(params) == 1)
+ psc_dma->slots |= 0x01000000;
+ else
+ psc_dma->slots |= 0x03000000;
+ }
+
+ spin_lock(&psc_dma->lock);
+ out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
+ spin_unlock(&psc_dma->lock);
+
+ return 0;
+}
+
+static int psc_ac97_hw_digital_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *cpu_dai)
+{
+ struct psc_dma *psc_dma = cpu_dai->private_data;
+
+ spin_lock(&psc_dma->lock);
+ if (params_channels(params) == 1)
+ out_be32(&psc_dma->psc_regs->ac97_slots, 0x01000000);
+ else
+ out_be32(&psc_dma->psc_regs->ac97_slots, 0x03000000);
+ spin_unlock(&psc_dma->lock);
+
+ return 0;
+}
+
+static int psc_ac97_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ struct snd_soc_pcm_runtime *rtd = substream->private_data;
+ struct psc_dma *psc_dma = rtd->dai->cpu_dai->private_data;
+
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_STOP:
+ if (substream->pstr->stream == SNDRV_PCM_STREAM_CAPTURE)
+ psc_dma->slots &= 0xFFFF0000;
+ else
+ psc_dma->slots &= 0x0000FFFF;
+
+ spin_lock(&psc_dma->lock);
+ out_be32(&psc_dma->psc_regs->ac97_slots, psc_dma->slots);
+ spin_unlock(&psc_dma->lock);
+ break;
+ }
+ return 0;
+}
+
+/* ---------------------------------------------------------------------
+ * ALSA SoC Bindings
+ *
+ * - Digital Audio Interface (DAI) template
+ * - create/destroy dai hooks
+ */
+
+/**
+ * psc_ac97_dai_template: template CPU Digital Audio Interface
+ */
+static struct snd_soc_dai_ops psc_ac97_analog_ops = {
+ .hw_params = psc_ac97_hw_analog_params,
+ .trigger = psc_ac97_trigger,
+};
+
+static struct snd_soc_dai_ops psc_ac97_digital_ops = {
+ .hw_params = psc_ac97_hw_digital_params,
+};
+
+struct snd_soc_dai psc_ac97_dai[] = {
+{
+ .name = "AC97",
+ .ac97_control = 1,
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 6,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S32_BE,
+ },
+ .capture = {
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S32_BE,
+ },
+ .ops = &psc_ac97_analog_ops,
+},
+{
+ .name = "SPDIF",
+ .ac97_control = 1,
+ .playback = {
+ .channels_min = 1,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_32000 | \
+ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+ .formats = SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_BE,
+ },
+ .ops = &psc_ac97_digital_ops,
+} };
+EXPORT_SYMBOL_GPL(psc_ac97_dai);
+
+
+
+/* ---------------------------------------------------------------------
+ * OF platform bus binding code:
+ * - Probe/remove operations
+ * - OF device match table
+ */
+static int __devinit psc_ac97_of_probe(struct of_device *op,
+ const struct of_device_id *match)
+{
+ int rc, i, id1, id2;
+ struct snd_ac97 ac97;
+ struct mpc52xx_psc __iomem *regs;
+
+ rc = mpc5200_audio_dma_create(op);
+ if (rc != 0)
+ return rc;
+
+ for (i = 0; i < ARRAY_SIZE(psc_ac97_dai); i++)
+ psc_ac97_dai[i].dev = &op->dev;
+
+ rc = snd_soc_register_dais(psc_ac97_dai, ARRAY_SIZE(psc_ac97_dai));
+ if (rc != 0) {
+ dev_err(&op->dev, "Failed to register DAI\n");
+ return rc;
+ }
+
+ psc_dma = dev_get_drvdata(&op->dev);
+ regs = psc_dma->psc_regs;
+ ac97.private_data = psc_dma;
+
+ for (i = 0; i < ARRAY_SIZE(psc_ac97_dai); i++)
+ psc_ac97_dai[i].private_data = psc_dma;
+
+ psc_dma->imr = 0;
+ out_be16(&psc_dma->psc_regs->isr_imr.imr, psc_dma->imr);
+
+ /* Configure the serial interface mode to AC97 */
+ psc_dma->sicr = MPC52xx_PSC_SICR_SIM_AC97 | MPC52xx_PSC_SICR_ENAC97;
+ out_be32(®s->sicr, psc_dma->sicr);
+
+ /* No slots active */
+ out_be32(®s->ac97_slots, 0x00000000);
+
+ /* AC97 clock is generated by the codec.
+ * Ensure that it starts ticking after codec reset.
+ */
+ rc = psc_ac97_cold_reset_check(&ac97);
+ if (rc != 0) {
+ dev_err(&op->dev, "AC97 codec failed to reset\n");
+ mpc5200_audio_dma_destroy(op);
+ return rc;
+ }
+
+ /* Go */
+ out_8(®s->command, MPC52xx_PSC_TX_ENABLE | MPC52xx_PSC_RX_ENABLE);
+
+ return 0;
+}
+
+static int __devexit psc_ac97_of_remove(struct of_device *op)
+{
+ return mpc5200_audio_dma_destroy(op);
+}
+
+/* Match table for of_platform binding */
+static struct of_device_id psc_ac97_match[] __devinitdata = {
+ { .compatible = "fsl,mpc5200-psc-ac97", },
+ { .compatible = "fsl,mpc5200b-psc-ac97", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, psc_ac97_match);
+
+static struct of_platform_driver psc_ac97_driver = {
+ .match_table = psc_ac97_match,
+ .probe = psc_ac97_of_probe,
+ .remove = __devexit_p(psc_ac97_of_remove),
+ .driver = {
+ .name = "mpc5200-psc-ac97",
+ .owner = THIS_MODULE,
+ },
+};
+
+/* ---------------------------------------------------------------------
+ * Module setup and teardown; simply register the of_platform driver
+ * for the PSC in AC97 mode.
+ */
+static int __init psc_ac97_init(void)
+{
+ return of_register_platform_driver(&psc_ac97_driver);
+}
+module_init(psc_ac97_init);
+
+static void __exit psc_ac97_exit(void)
+{
+ of_unregister_platform_driver(&psc_ac97_driver);
+}
+module_exit(psc_ac97_exit);
+
+MODULE_AUTHOR("Jon Smirl <jonsmirl@xxxxxxxxx>");
+MODULE_DESCRIPTION("mpc5200 AC97 module");
+MODULE_LICENSE("GPL");
+
diff --git a/sound/soc/fsl/mpc5200_psc_ac97.h b/sound/soc/fsl/mpc5200_psc_ac97.h
new file mode 100644
index 0000000..4bc18c3
--- /dev/null
+++ b/sound/soc/fsl/mpc5200_psc_ac97.h
@@ -0,0 +1,15 @@
+/*
+ * Freescale MPC5200 PSC in AC97 mode
+ * ALSA SoC Digital Audio Interface (DAI) driver
+ *
+ */
+
+#ifndef __SOUND_SOC_FSL_MPC52xx_PSC_AC97_H__
+#define __SOUND_SOC_FSL_MPC52xx_PSC_AC97_H__
+
+extern struct snd_soc_dai psc_ac97_dai[];
+
+#define MPC5200_AC97_NORMAL 0
+#define MPC5200_AC97_SPDIF 1
+
+#endif /* __SOUND_SOC_FSL_MPC52xx_PSC_AC97_H__ */
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