On 04/02/2009 12:34 PM, Mark Brown wrote: > On Thu, Apr 02, 2009 at 10:39:12AM +0300, Jarkko Nikula wrote: >> My two cents: It supports different sampling rates for ADC and DAC but >> I don't believe there is practical use or HW doing this. In this setup >> there is separate word clock signal on GPIO1 for ADC. > > Hrm, that's fairly common for hardware - even with shared LRCLK many > devices will be able to support asymmetric rates providing there are > enough BCLKs to drive the data. Presumably the only limit in the codec > itself is going to be that whatever the PLL is set for will be the > maximum. It's only the tlv320aic33 that has GPIO pins. On the other supported devices the datasheet says on register 98: "Reserved. Write only 0 to these bits" While we're at it, there are other registers where we are already writing values != 0 which are not allowed on aic31 and aic32. Daniel -- Dipl.-Math. Daniel Glöckner, emlix GmbH, http://www.emlix.com Fon +49 551 30664-0, Fax -11, Bahnhofsallee 1b, 37081 Göttingen, Germany Geschäftsführung: Dr. Uwe Kracke, Dr. Cord Seele, Ust-IdNr.: DE 205 198 055 Sitz der Gesellschaft: Göttingen, Amtsgericht Göttingen HR B 3160 emlix - your embedded linux partner _______________________________________________ Alsa-devel mailing list Alsa-devel@xxxxxxxxxxxxxxxx http://mailman.alsa-project.org/mailman/listinfo/alsa-devel
