On Tuesday 27 January 2009 22:32:11 Vasily Khoruzhick wrote: > On 27 January 2009 21:49:01 pHilipp Zabel wrote: > > The uda1380 data sheet says that the reset time should be at least 1 > > µs - could that be a problem? > > > > regards > > Philipp > > Nope, added mdelay(10) in reset sequence, but it didn't help. > > Regards > Vasily Here's patch that fixes 2nd bug I've mentioned (there's a sound only on second and later aplay). It's bug in uda1380 driver (probably, just a typo), driver switches to WSPLL in uda1380_pcm_prepare even if SYSCLK was chosen (uda1380_pcm_prepare modifies UDA1380_CLK register before flushing reg cache, but doesn't restore its value later) One more question: it seems that my rx1950 clocked in a way that I can't get precise divisor for 44100 and 22050 rates, but uda1380 driver propose them (look UDA1380_RATES define and struct snd_soc_dai uda1380_dai[]. How to exclude all rates except 16000 and 48000? Should I declare my own snd_soc_dai and copy necessary members from uda1380's one? Regards Vasily
From ad025e64d006dc86b7a669b8f5ab611b0b33b292 Mon Sep 17 00:00:00 2001 From: Vasily Khoruzhick <anarsoul@xxxxxxxxx> Date: Tue, 3 Feb 2009 01:34:09 +0200 Subject: [PATCH] Fix typo in uda1380 driver Signed-off-by: Vasily Khoruzhick <anarsoul@xxxxxxxxx> --- sound/soc/codecs/uda1380.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/sound/soc/codecs/uda1380.c b/sound/soc/codecs/uda1380.c index a69ee72..a4d32b1 100644 --- a/sound/soc/codecs/uda1380.c +++ b/sound/soc/codecs/uda1380.c @@ -433,7 +433,7 @@ static int uda1380_pcm_prepare(struct snd_pcm_substream *substream) } /* FIXME enable DAC_CLK */ - uda1380_write(codec, UDA1380_CLK, clk | R00_DAC_CLK); + uda1380_write(codec, UDA1380_CLK, clk); return 0; } -- 1.6.1.1
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