Add bindings for the Multi-Channel I2S controller of Cadence on the StarFive JH8100 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> --- .../bindings/sound/cdns,jh8100-i2s.yaml | 100 ++++++++++++++++++ 1 file changed, 100 insertions(+) create mode 100644 Documentation/devicetree/bindings/sound/cdns,jh8100-i2s.yaml diff --git a/Documentation/devicetree/bindings/sound/cdns,jh8100-i2s.yaml b/Documentation/devicetree/bindings/sound/cdns,jh8100-i2s.yaml new file mode 100644 index 000000000000..5d95d9ab3e45 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cdns,jh8100-i2s.yaml @@ -0,0 +1,100 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cdns,jh8100-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cadence multi-channel I2S controller for StarFive JH8100 SoC + +description: | + The Cadence I2S Controller implements a function of the multi-channel + (up to 8-channel) bus. It combines functions of a transmitter and a receiver. + It is used in the StarFive JH8100 SoC. + +maintainers: + - Xingyu Wu <xingyu.wu@xxxxxxxxxxxxxxxx> + - Walker Chen <walker.chen@xxxxxxxxxxxxxxxx> + +properties: + compatible: + const: starfive,jh8100-i2s + + reg: + maxItems: 1 + + interrupts: + description: | + The interrupt line number for the I2S controller. Add this + parameter if the I2S controller that you are using does not + support DMA. + maxItems: 1 + + clocks: + items: + - description: Bit clock + - description: Main ICG clock + - description: Inner master clock + + clock-names: + items: + - const: bclk + - const: icg + - const: mclk_inner + + resets: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + minItems: 1 + + dma-names: + items: + - const: tx + - const: rx + minItems: 1 + + cdns,i2s-max-channels: + description: | + Number of I2S max stereo channels supported by the hardware. + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 8 + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + +oneOf: + - required: + - dmas + - dma-names + - required: + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2s@122b0000 { + compatible = "starfive,jh8100-i2s"; + reg = <0x122b0000 0x1000>; + clocks = <&syscrg_ne 133>, + <&syscrg_ne 170>, + <&syscrg 50>; + clock-names = "bclk", "icg", + "mclk_inner"; + resets = <&syscrg_ne 43>; + dmas = <&dma 7>, <&dma 6>; + dma-names = "tx", "rx"; + cdns,i2s-max-channels = <2>; + #sound-dai-cells = <0>; + }; -- 2.25.1
