Hi Richard,
richard@xxxxxx wrote on Mon, 18 Dec 2023 23:10:20 +0100 (CET):
> ----- Ursprüngliche Mail -----
> > Von: "Amit Kumar Mahapatra" <amit.kumar-mahapatra@xxxxxxx>
>
> > This patch series updated the spi-nor, spi core and the AMD-Xilinx GQSPI
> > driver to add stacked and parallel memories support.
>
> I wish the series had a real cover letter which explains the big picture
> in more detail.
>
> What I didn't really get so far, is it really necessary to support multiple
> chip selects within a single mtd?
> You changes introduce hard to maintain changes into the spi-nor/mtd core code
> which alert me.
> Why can't we have one mtd for each cs and, if needed, combine them later?
> We have drivers such as mtdconcat for reasons.
The Xilinx SPI controller is a bit convoluted, there are two ways to
address the bits in a memory:
* Either your extend the memory range with the second chip "on
top" of the first (which would typically be a mtd-concat use case)
* Or you use the two chips in parallel and you store the even bits
in one device (let's say cs0) and the odd bits in the other (cs1).
Extending mtd-concat for this might be another solution, I don't know
how feasible it would be.
Maybe these bindings will help understanding the logic:
e2edd1b64f1c ("spi: dt-bindings: Describe stacked/parallel memories modes")
eba5368503b4 ("spi: dt-bindings: Add an example with two stacked flashes")
However I agree the changes will likely be hard to maintain given the
complexity brought with such a different controller.
Thanks,
Miquèl
