On Mon, 25 Sep 2023 10:21:15 +0200 Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote: > On 25/09/2023 10:17, Herve Codina wrote: > > Hi Krzysztof, > > > > On Sat, 23 Sep 2023 19:39:49 +0200 > > Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> wrote: > > > >> On 22/09/2023 09:58, Herve Codina wrote: > >>> The QMC (QUICC mutichannel controller) is a controller present in some > >>> PowerQUICC SoC such as MPC885. > >>> The QMC HDLC uses the QMC controller to transfer HDLC data. > >>> > >>> Additionally, a framer can be connected to the QMC HDLC. > >>> If present, this framer is the interface between the TDM bus used by the > >>> QMC HDLC and the E1/T1 line. > >>> The QMC HDLC can use this framer to get information about the E1/T1 line > >>> and configure the E1/T1 line. > >>> > >>> Signed-off-by: Herve Codina <herve.codina@xxxxxxxxxxx> > >>> --- > >>> .../soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml | 24 +++++++++++++++++++ > >>> 1 file changed, 24 insertions(+) > >>> > >>> diff --git a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > >>> index 82d9beb48e00..61dfd5ef7407 100644 > >>> --- a/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > >>> +++ b/Documentation/devicetree/bindings/soc/fsl/cpm_qe/fsl,cpm1-scc-qmc.yaml > >>> @@ -101,6 +101,27 @@ patternProperties: > >>> Channel assigned Rx time-slots within the Rx time-slots routed by the > >>> TSA to this cell. > >>> > >>> + compatible: > >>> + const: fsl,qmc-hdlc > >> > >> Why this is not a device/SoC specific compatible? > > > > This compatible is present in a QMC channel. > > The parent node (the QMC itself) contains a compatible with device/SoC: > > --- 8< --- > > compatible: > > items: > > - enum: > > - fsl,mpc885-scc-qmc > > - fsl,mpc866-scc-qmc > > - const: fsl,cpm1-scc-qmc > > --- 8< --- > > > > At the child level (ie QMC channel), I am not sure that adding device/SoC > > makes sense. This compatible indicates that the QMC channel is handled by > > the QMC HDLC driver. > > At this level, whatever the device/SoC, we have to be QMC compliant. > > > > With these details, do you still think I need to change the child (channel) > > compatible ? > > From OS point of view, you have a driver binding to this child-level > compatible. How do you enforce Linux driver binding based on parent > compatible? I looked at your next patch and I did not see it. We do not need to have the child driver binding based on parent. We have to ensure that the child handles a QMC channel and the parent provides a QMC channel. A QMC controller (parent) has to implement the QMC API (include/soc/fsl/qe/qmc.h) and a QMC channel driver (child) has to use the QMC API. Best regards, Hervé > > Best regards, > Krzysztof >
